Features Complies with OpenLDI specification for digital display interfaces 32.5 to 112/170MHz clock support for DS90C387, 40 to 112MHz clock support for DS90CF388 Supports SVGA through QXGA panel resolutions Drives long, low cost cables Up to 5.38Gbps bandwidth Pre-emphasis reduces cable loading effects DC Balance data transmission provided by transmitter reduces ISI distortion Cable Deskew of +/-1 LVDS data bit time (up to 80 MHz Clock Rate) of pair-to-pair skew at receiver inputs; intra-pair skew tolerance of 300ps Dual pixel architecture supports interface to GUI and timing controller; optional single pixel transmitter inputs support single pixel GUI interface Transmitter rejects cycle-to-cycle jitter 5V tolerant on data and control input pins Programmable transmitter data and control strobe select (rising or falling edge strobe) Backward compatible configuration select with FPD-Link Optional second LVDS clock for backward compatibility w/ FPD-Link Support for two additional user-defined control signals in DC Balanced mode Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard Description The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data streams. Control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent during blanking intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a total throughput of 5.38Gbps (672 Megabytes per second). Two other modes are also supported. 24-bit color data (single pixel) can be clocked into the transmitter at a maximum rate of 170MHz. In this mode, the transmitter provides single-to-dual pixel conversion, and the output LVDS clock rate is 85MHz maximum. The third mode provides inter-operability with FPD-Link devices. The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum pixel clock rate is increased to 112 (170) MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew of up to +/-1 LVDS data bit time (up to 80 MHz Clock Rate). These three enhancements allow cables 5+ meters in length to be driven. This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the "Applications Information" section of this datasheet.

	Block Diagram click for larger image

Parameters Values Function Receiver Color Depth 24 bpp Pixel Clock Max 112 MHz Pixel Clock Min 40 MHz Output Compatibility LVCMOS Total Throughput 6272 Mbps Payload/Channel 784 Mbps Supply Voltage 3.3 Volt Temperature Min -10 deg C Temperature Max 70 deg C Sensing & Imaging Yes DisplayType FPD

Datasheets

Title		Size	Date	Other Language
	DS90CF388 +3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA	916 Kbytes	3-Feb-06	日本語

Application Notes

Title		Size	Date	Other Language
	AN-1032: Application Note 1032 An Introduction to FPD-Link	177 Kbytes	3-Apr-09	日本語
	AN-1163: Application Note 1163 TFT Data Mapping for LDI Dual Pixel Application - Alternate A - Color Map	13 Kbytes	15-May-04
	AN-1056: Application Note 1056 STN Application Using FPD-Link	46 Kbytes	4-Oct-04	日本語
	AN-1085: Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines	304 Kbytes	4-Oct-04	日本語
	AN-1127: Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperability with FPD-Link	25 Kbytes	4-Oct-04

Other Technical Documents

Title		Type	Date
	LVDS goes the distance!	App Note	2003-02-17

Part Number(s) (NSID)	Top View	Availability	Current Reported Stock	Budgetary Pricing	Pack Size
DS90CF388VJD/NOPB DS90CF388VJD RoHS Status	TQFP	Full production Lead Time: 6 weeks	Distributor Region Qty ARROW Worldwide 15 AVNET-EM Worldwide 41 DIGI-KEY Worldwide 169 FARNELL Europe and Asia 10 MOUSER Worldwide 70 NEWARK Americas 102 TAYLOR Americas 105	$4.91 each at 1K+ pcs	tray of 90
DS90CF388VJDX/NOPB DS90CF388VJDX RoHS Status	TQFP	Full production Lead Time: 6 weeks	Distributor Region Qty DIGI-KEY Worldwide 0	$4.91 each at 1K+ pcs	reel of 1000

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for DS90CF388.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for DS90CF388 is located at RoHS Status.

Part Number(s) (NSID)	Description	Availability	Current Reported Stock	Budgetary Pricing	Pack Size
LDI3V8BT-112	Evaluation Kit for DS90C387(A) and DS90CF388(A) Dual Pixel LDI Serializer and Deserializer LVDS Chipset	Preliminary	Distributor Region Qty DIGI-KEY Worldwide 0	$253.00 each	1
Description: The LDI3V8BT-112 is an evaluation kit designed to demonstrate performance and capabilities of the DS90C387 and DS90CF388 and DS90C387A and DS90CF388A Open LDI Serializer/Deserializer Chipsets. The DS90C387 Serializer board accepts LVCMOS input signals and provides serialized FPD-Link LVDS data pairs as an output. The DS90CF388 Deserializer board accepts the FPD-Link LVDS serialized data streams and converts the data back into parallel LVCMOS signals and clock. Flat Ribbon cable is provided as a generic medium for the high speed data link. Jumpers and switches on the boards can be configured for evaluation of chipset features. Contents: One Serializer board with IDC connectors on TX input with DS90C387 One Deserializer board with IDC connectors on RX output with DS90CF388 One 2- meter 3 M MDR LVDS Cable Interface Evaluation Kit Documentation What the user needs to provide: A source of RGB bus and clock - for example a video generator LCD panel and interface from deserializer board to the panel itself, or a test equipment Power supply for the both boards

National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C1) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/en/packaging/greennopb.html. Lead free products are RoHS compliant.

Lead Free product status is available through the search tool located here

Part Number(s) (NSID)	Weight (milligrams)	Type	Pins	MSL Rating	Peak Reflow	RoHS Status	CAD Symbols	Models	Package Marking Format
DS90CF388VJD/NOPB DS90CF388VJD	508.38 510.01	TQFP	100	3 3	260 260	Detail	N/A	ibis file	NS2ZXYYTTE# DS90CF388VJD BBBBB
DS90CF388VJDX/NOPB DS90CF388VJDX	508.38 510.01	TQFP	100	3 3	260 260	Detail	N/A	N/A	NS2ZXYYTTE# DS90CF388VJD BBBBB

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for DS90CF388.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for DS90CF388 is located at RoHS Status.

Design Tools

Title	Size	Date
Evaluation Kit for DS90C387(A) and DS90CF388(A) Dual Pixel LDI Serializer and Deserializer LVDS Chipset

CAD Symbols and Models N/A

Models ibis file

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90CF388VJD	.35	0	20275	0	0	1515000	3	429885386
DS90CF388VJDX	.35	0	20275	0	0	1515000	3	429885386

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

All information pertaining to the RoHS Compliance Standard can be found at http://www.national.com/en/packaging/leadfree.html.

Moisture Sensitivity Level Data for DS90CF388.

A RoHS compliance or an IPC 1752 report can be acquired at http://www.national.com/en/packaging/greennopb.html.

National's certificate of product compliance for DS90CF388 is located at RoHS Status.