Features • 20 to 65 MHz shift clock support • 50% duty cycle on receiver output clock • Best–in–Class Set & Hold Times on RxOUTPUTs • Rx power consumption <142 mW (typ) @65MHz Grayscale • Rx Power-down mode <200μW (max) • ESD rating >7 kV (HBM), >700V (EIAJ) • Supports VGA, SVGA, XGA and Dual Pixel SXGA. • PLL requires no external components • Compatible with TIA/EIA-644 LVDS standard • Low profile 56-lead or 48-lead TSSOP package • DS90CF384A is also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package Description The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF364A that converts the three LVDS data streams (Up to 1.3 Gbps throughput or 170 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers' outputs are Falling edge strobe. A Rising edge or Falling edge strobe transmitter (DS90C383A/DS90C363A) will interoperate with a Falling edge strobe Receiver without any translation logic. The DS90CF384A / DS90CF364A devices are enhanced over prior generation receivers and provided a wider data valid time on the receiver output. The DS90CF384A is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the 56L TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

Also Recommended DS90CF366▲ 85 Mhz Transmit Clock Frequency MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image	Block Diagram *click for larger image

Datasheet

Title		Size	Date	Other Language
	DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link—65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link—65 MHz	445 Kbytes	12-Jul-07	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1085: Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines	304 Kbytes	4-Oct-04	日本語

More Application Notes

Title		Size	Date	Other Language
	AN-1085: Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines	304 Kbytes	4-Oct-04	日本語

Design Tools

Title	Size	Date
Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90CF364AMTD	.35	0	19690	0	0	1425000	3	404347640
DS90CF364AMTDX	.35	0	19690	0	0	1425000	3	404347640

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.