Features • Pin-to-pin compatible to DS90C363, DS90C363A and DS90C365 . • No special start-up sequence required between clock/data and /PD pins. Input signals (clock and data) can be applied either before or after the device is powered. • Support Spread Spectrum Clocking up to 100kHz frequency modulation & deviations of ±2.5% center spread or -5% down spread. • “Input Clock Detection” feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high. • 18 to 87.5 MHz shift clock support • Tx power consumption < 146 mW (typ) @ 87.5 MHz Grayscale • Tx Power-down mode < 37 uW (typ) • Supports VGA, SVGA, XGA, SXGA(dual pixel), SXGA+(dual pixel), UXGA(dual pixel). • Narrow bus reduces cable size and cost • Up to 1.785 Gbps throughput • Up to 223.125 Megabytes/sec bandwidth • 345 mV (typ) swing LVDS devices for low EMI • PLL requires no external components • Compliant to TIA/EIA-644 LVDS standard • Low profile 48-lead TSSOP package Description The DS90C365A is a pin to pin compatible replacement for DS90C363, DS90C363A and DS90C365. The DS90C365A has additional features and improvements making it an ideal replacement for DS90C363, DS90C363A and DS90C365. family of LVDS Transmitters. The DS90C365A transmitter converts 21 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fourth LVDS link. Every cycle of the transmit clock 21 bits RGB of input data are sampled and transmitted. At a transmit clock frequency of 87.5 MHz, 21 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 612.5 Mbps per LVDS data channel. Using a 87.5 MHz clock, the data throughput is 229.687 Mbytes/sec. This transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe FPDLink Receiver without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces with added Spead Spectrum Clocking support..

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Datasheet

Title		Size	Date	Other Language
	DS90C365A +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz	327 Kbytes	6-Aug-08

Featured Application Notes

Title		Size	Date	Other Language
	AN-1909: Application Note 1909 DS15BA101 and DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES	360 Kbytes	2-Mar-09	中文

More Application Notes

Title		Size	Date	Other Language
	AN-1127: Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperability with FPD-Link	25 Kbytes	4-Oct-04

Design Tools

Title	Size	Date
"Evaluation Kit for FPD-Link 20-85MHz 3.3V, 24 bit"

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90C365AMT	CMOS7	0	18406	0	0	1089000	4	309006723
DS90C365AMTX	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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