Features • 5 to 12.5 Gbps Operation • No Power or Ground Required • Equalization effective anywhere in data path • Equalizes CML, LV-PECL, LVDS signals • Symmetric I/O structures provide equal boost for bi-directional operation • 7 dB Maximum Boost • Code independent, 8b/10b or Scrambled • Supports both bi-level and multi-level signaling • Extends reach over backplanes and cables • Compatible with PCI-Express Gen1 and Gen2 • Compatible with XAUI • Will operate in series with existing active Equalizer • Easy to handle 6 pin LLP Description National’s Power-saver equalizer compensates for transmission medium losses and minimizes medium-induced deterministic jitter. Performance is guaranteed over the full range of 5 to 12.5 Gbps. The DS80EP100 requires no power to operate. The equalizer operates anywhere in the data path to minimize media-induced deterministic jitter in both FR4 traces and cable applications. Symmetric I/O structures support full duplex or half duplex applications. Linear compensation is provided independent of line coding or protocol. The device is ideal for both bi-level and multi-level signaling. The equalizer is available in a 6 pin leadless LLP package with a space saving 2.2 mm X 2.5 mm footprint. This tiny package provides maximum flexibility in placement and routing of the Power-saver equalizer.

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Typical Application *click for larger image	Block Diagram click for larger image
Typical Performance *click for larger image

Datasheet

Title		Size	Date	Other Language
	DS80EP100 5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables	4106 Kbytes	20-May-08	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-214: Application Note 214 Transmission Line Drivers and Receivers for TIA/EIA Standards RS‐422 and RS‐423	338 Kbytes	4-Oct-04

More Application Notes

Title		Size	Date	Other Language
	AN-22: Application Note 22 Integrated Circuits for Digital Data Transmission	445 Kbytes	2-Oct-02

Design Tools

Title	Size	Date
6.4 Gbps Quad Equalizer Evaluation Board User Guide 12.5 Gbps Power-saver Equalizer Eval Board	87 Kbytes	4-Sep-2007

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS80EP100SD	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS80EP100SDX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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