Features • Equalizes up to 24 dB loss at 10 Gbps • Equalizes up to 22 dB loss at 6.4 Gbps • 8 levels of programmable equalization • Settable through control pins or SMBus interface • Operates up to 10 Gbps with 30” FR4 traces • Operates up to 6.4 Gbps with 40” FR4 traces • 0.175 UI residual deterministic jitter at 6.4 Gbps with 40” FR4 traces • Single 2.5V or 3.3V power supply • Signal Detect for individual channels • Standby mode for individual channels • Supports AC or DC-Coupling with wide input common-mode • Low power consumption: 375 mW Typ at 2.5V • Small 7 mm x 7 mm 48-pin LLP package • 9 kV HBM ESD Rating • -40 to 85°C operating temperature range Description The DS64EV400 programmable quad equalizer provides compensation for transmission medium losses and reduces the medium-induced deterministic jitter for four NRZ data channels. The DS64EV400 is optimized for operation up to 10 Gbps for both cables and FR4 traces. Each equalizer channel has eight levels of input equalization that can be programmed by three control pins, or individually through a Serial Management Bus (SMBus) interface. The equalizer supports both AC and DC-coupled data paths for long run length data patterns such as PRBS-31, and balanced codes such as 8b/10b. The device uses differential current-mode logic (CML) inputs and outputs. The DS64EV400 is available in a 7 mm x 7 mm 48-pin leadless LLP package. Power is supplied from either a 2.5V or 3.3V supply.

App Diagram MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image App Diagram	Block Diagram *click for larger image Figure 9
Typical Performance *click for larger image Figure 16

Datasheet

Title		Size	Date	Other Language
	DS64EV400 Programmable Quad Equalizer	1497 Kbytes	18-Apr-08

Featured Application Notes

Title		Size	Date	Other Language
	AN-1399: Application Note 1399 Enabling Redundancy in Multi-Gigabit Links with DS40MB200 Mux/Buffer	1440 Kbytes	17-Oct-05	日本語 中文
	AN-1398: Application Note 1398 Printed Circuit Board Design Techniques for DS40MB200	1007 Kbytes	21-Oct-05	日本語 中文
	AN-1389: Application Note 1389 Setting Pre-Emphasis Level for DS40MB200 Dual 4Gb/s Mux/Buffer	1646 Kbytes	21-Oct-05	日本語 中文

More Application Notes

Title		Size	Date	Other Language
	AN-514: Application Note 514 Timing Analysis of Synchronous and Asynchronous Buses	153 Kbytes	2-Mar-99	日本語

Design Tools

Title	Size	Date
6.4 Gbps Quad Equalizer Evaluation Board User Guide	2472 Kbytes	9-Oct-2007

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS64EV400SQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS64EV400SQX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.