Features • Quad lane bi-directional transceiver up to 6.4 Gbps rate • Signal conditioning on input and output for extended reach • Adjustable receive equalization up to +33 dB gain • Adjustable transmit de-emphasis up to −12 dB • Adjustable transmit VOD (600 mVp-p to 1200 mVp-p) • <0.25 UI of residual DJ at 6.4 Gbps with 40” FR4 trace • Automatic de-emphasis scaling based on rate detect • SATA/SAS: OOB signal pass-through, • <3 ns (typ) envelope distortion • Adjustable electrical IDLE detect threshold • Low power (100 mW/channel), per-channel power down • Programmable via pin selection or SMBus interface • Single supply operation at 2.5V ±5% • >6 kV HBM ESD Rating • 3.3V LVCMOS input tolerant for SMBus interface • High speed signal flow–thru pinout package: 54-pin LLP (10 mm x 5.5 mm) Description The DS64BR401 is a quad lane bi-directional signal conditioning transceiver suitable for 6.0/3.0/1.5 Gbps SATA/SAS and other high-speed bus applications with data rates up to 6.4 Gbps. The device performs both receive equalization and transmit de-emphasis on each of its 8 channels to compensate for channel loss, allowing maximum flexibility of physical placement within a system. The receiver's continuous time linear equalizer (CTLE) provides a boost of up to +33 dB at 3 GHz and is capable of opening an input eye that is completely closed due to inter-symbol interference (ISI) induced by the interconnect medium. The transmitter features a programmable output de-emphasis driver and allows amplitude voltage levels to be selected from 600 mVp-p to 1200 mVp-p to suit multiple application scenarios. This Low Power Differential Signaling (LPDS) output driver is a power efficient implementation that maintains compatibility with AC coupled CML receiver. The programmable settings can be applied via pin settings or SMBus interface. To enable seamless upgrade from SAS/SATA 3.0 Gbps to 6.0 Gbps data rates without compromising physical reach, DS64BR401 automatically detects the incoming data rate and selects the optimal de-emphasis pulse width. The device detects the out-of-band (OOB) idle and active signals of the SAS/SATA specification and passes through with minimum signal distortion. With a typical power consumption of 200 mW/lane (100 mW/channel) at 6.4 Gbps, and control to turn-off unused channels, the DS64BR401 is part of National's PowerWise family of energy efficient devices. Applications • SATA (1.5, 3.0 and 6 Gbps) • SAS (1.5, 3.0 and 6 Gbps) • XAUI (3.125 Gbps), RXAUI (6.25 Gbps) • sRIO – Serial Rapid I/O • Fibre Channel (4.25 Gbps) • 10GBase-CX4, InfiniBand 4x (SDR & DDR) • QSFP active copper cable modules • High-speed active cable and FR-4 backplane traces

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Datasheet

Title		Size	Date	Other Language
	DS64BR401 Quad Bi-Directional Transceiver with Equalization and De-Emphasis	1960 Kbytes	26-Oct-09

Featured Application Notes

Title		Size	Date	Other Language
	AN-1399: Application Note 1399 Enabling Redundancy in Multi-Gigabit Links with DS40MB200 Mux/Buffer	1440 Kbytes	17-Oct-05	日本語 中文
	AN-1398: Application Note 1398 Printed Circuit Board Design Techniques for DS40MB200	1007 Kbytes	21-Oct-05	日本語 中文
	AN-1389: Application Note 1389 Setting Pre-Emphasis Level for DS40MB200 Dual 4Gb/s Mux/Buffer	1646 Kbytes	21-Oct-05	日本語 中文

More Application Notes

Title		Size	Date	Other Language
	AN-514: Application Note 514 Timing Analysis of Synchronous and Asynchronous Buses	153 Kbytes	2-Mar-99	日本語

Design Tools

Title	Size	Date
DS64BR401EVK Evaluation Board User Guide	3420 Kbytes	26-Jun-2009

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS64BR401SQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS64BR401SQE	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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