Features • Input and Output signal conditioning increases PCIe reach in backplanes and cables • 0.09 UI of residual deterministic jitter at 5Gbps after 42” of FR4 (with Input EQ) • 0.11 UI of residual deterministic jitter at 5Gbps after 7m of PCIe Cable (with Input EQ) • 0.09 UI of residual deterministic jitter at 5Gbps with 28” of FR4 (with Output DE) • 0.13 UI of residual deterministic jitter at 5Gbps with 7m of PCIe Cable (with Output DE) • Adjustable Transmit VOD 800 to 1200mVp-p • Automatic power management on an individual lane basis via SMBus • Adjustable electrical idle detect threshold. • Data rate optimized 3-stage equalization to 26 dB gain • Data rate optimized 6-level 0 to 12 dB transmit de-emphasis • Flow-thru pinout in 10mmx5.5mm 54-pin leadless LLP package • Single supply operation at 2.5V • >6kV HBM ESD rating • -10 to 85°C operating temperature range Description The DS50PCI401 is a low power, 4 lane bidirectional buffer/equalizer designed specifically for PCI Express Gen1 and Gen2 applications. The device performs both receive equalization and transmit de-emphasis, allowing maximum flexibility of physical placement within a system. The receiver is capable of opening an input eye that is completely closed due to inter-symbol interference (ISI) induced by the interconnect medium. The transmitter de-emphasis level can be set by the user depending on the distance from the DS50PCI401 to the PCI Express endpoint. The DS50PCI401 contains PCI Express specific functions such as Transmit Idle, RX Detection, and Beacon signal pass through. The device will change the load impedance on its input pins based on the state of RXDETA/B inputs detection. An internal rate detection circuit is included to detect if an incoming data stream is at Gen2 data rates, and adjusts the de-emphasis on it's output accordingly. The signal conditioning provided by the device allows systems to upgrade from Gen1 data rates to Gen2 without reducing their physical reach. This is true for FR4 applications such as backplanes, as well as cable interconnect.

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Datasheet

Title		Size	Date	Other Language
	DS50PCI401 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Transceiver with Equalization and De-Emphasis	921 Kbytes	25-Aug-09

Featured Application Notes

Title		Size	Date	Other Language
	AN-1399: Application Note 1399 Enabling Redundancy in Multi-Gigabit Links with DS40MB200 Mux/Buffer	1440 Kbytes	17-Oct-05	日本語 中文
	AN-1398: Application Note 1398 Printed Circuit Board Design Techniques for DS40MB200	1007 Kbytes	21-Oct-05	日本語 中文
	AN-1389: Application Note 1389 Setting Pre-Emphasis Level for DS40MB200 Dual 4Gb/s Mux/Buffer	1646 Kbytes	21-Oct-05	日本語 中文

More Application Notes

Title		Size	Date	Other Language
	AN-514: Application Note 514 Timing Analysis of Synchronous and Asynchronous Buses	153 Kbytes	2-Mar-99	日本語

Design Tools

Title	Size	Date
DS50PCI401EVK Evaluation Board User Guide	2462 Kbytes	26-Jun-2009

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS50PCI401SQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS50PCI401SQE	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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