Features • PCI Express compatible Equalizer • Automatic power management on an individual lane basis • Data rate optimized equalization • Operates over 7 meter of 24 AWG PCI Express Cables up to 8 Gbps • Typical residual deterministic jitter: •  0.18 UI @ 8 Gbps w/ 30” of FR4 •  0.18 UI @ 5 Gbps w/ 40” of FR4 •  0.16 UI @ 2.5 Gbps w/ 40” of FR4 • 8 kV HBM ESD protection • -40 to 85°C operating temperature range • 7 mm x 7 mm 48-pin leadless LLP package • Single power supply of either 3.3V or 2.5V • Low power (typically 95 mW per channel at 2.5V VDD) Description The DS50EV401 is a low power, programmable equalizer specifically designed for PCI Express applications. The device provides 2 equalization settings to reduce inter-symbol interference (ISI) induced by a variety of interconnect media. One setting is optimized for PCIe Gen1 and Gen2 applications; the other is optimized for future Gen3 data rates. In all modes, the equalizer can operate, error free, with an input eye that is completely closed by interconnect ISI. The MODE, allows the user to select between equalization settings for 8Gbps operation or 2.5Gbps / 5.0Gbps operation. The DS50EV401 enables PCI Express compatible link extension by supporting transmit electrical idle, and Beacon signal pass through on a per lane basis. Current-mode logic (CML) is used on both input and output ports, which provide constant 50 ohm single-ended impedance to AC ground. Differential signaling is implemented through out the entire signal path to minimize supply induced jitter. The DS50EV401 is available in a 7mm x 7mm 48-pin leadless LLP package, and is powered from a single power supply of either 3.3 or 2.5V.

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Typical Application click for larger image Figure 7	Block Diagram click for larger image Figure 14

Datasheet

Title		Size	Date	Other Language
	DS50EV401 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad PCI Express Cable and Backplane Equalizer	1497 Kbytes	17-Jul-08

Featured Application Notes

Title		Size	Date	Other Language
	AN-1399: Application Note 1399 Enabling Redundancy in Multi-Gigabit Links with DS40MB200 Mux/Buffer	1440 Kbytes	17-Oct-05	日本語 中文
	AN-1398: Application Note 1398 Printed Circuit Board Design Techniques for DS40MB200	1007 Kbytes	21-Oct-05	日本語 中文
	AN-1389: Application Note 1389 Setting Pre-Emphasis Level for DS40MB200 Dual 4Gb/s Mux/Buffer	1646 Kbytes	21-Oct-05	日本語 中文

More Application Notes

Title		Size	Date	Other Language
	AN-514: Application Note 514 Timing Analysis of Synchronous and Asynchronous Buses	153 Kbytes	2-Mar-99	日本語

Design Tools

Title	Size	Date
DS50EV401-EVK User Guide	181 Kbytes	18-Apr-2008

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS50EV401SQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS50EV401SQE	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS50EV401SQX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.