Features • 5-bit DDR LVDS parallel data interface • Programmable transmit de-emphasis • Configurable output levels (VOD) • Selectable DC-balanced encoder • Selectable data scrambler • Remote Sense for automatic detection and negotiation of link status • On chip LC VCOs • Redundant serial output (ELX device only) • Data valid signaling to assist with synchronization of multiple receivers • Supports AC- and DC-coupled signaling • Integrated CML and LVDS terminations • Configurable PLL loop bandwidth • Programmable output termination (50Ω or 75Ω). • Built-in test pattern generator • Loss of lock and error reporting • Configurable via SMBus • 48-pin LLP package with exposed DAP Description The DS32EL0421/ DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface. The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps. The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path. The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins. Key Specification • 1.25 to 3.125 Gbps serial data rate • 125 to 312.5 MHz DDR parallel clock • -40° to +85°C temperature range • >8 kV ESD (HBM) protection • Low Intrinsic Jitter — 35ps at 3.125 Gbps

Also Recommended DS32ELX0124▲ Matching 3.125 Gbps DeSerializer With 5-bit DDR LVDS Interface Fig 1 Typ App Diagram MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application click for larger image Fig 1 Typ App Diagram	Connection Diagram click for larger image EL Pin Diagram
Typical Performance click for larger image Typ Perf 1.25G_Differential

Datasheet

Title		Size	Date	Other Language
	DS32EL0421 , DS32ELX0421 125 – 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface	1304 Kbytes	2-Jun-09

Featured Application Notes

Title		Size	Date	Other Language
	AN-1979: Application Note 1979 LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers	146 Kbytes	2-Jul-09
	AN-1887: Application Note 1887 Expanding the Payload with National’s FPGA-Link DS32ELX0421 and DS32ELX0124 Serializer and Deserializer	122 Kbytes	12-Sep-08

More Application Notes

Title		Size	Date	Other Language
	AN-903: Application Note 903 A Comparison of Differential Termination Techniques	196 Kbytes	2-Oct-02
	AN-967: Application Note 967 LocalTalk Physical Layer Alternatives	58 Kbytes	5-Oct-98

Design Tools

Title	Size	Date
Interfacing National's FPGA-Link Ser/Des with Altera Cyclone III FPGAs	135 Kbytes	21-Jul-2009
Article - FPGA-Link SerDes Reference Design

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS32ELX0421SQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS32ELX0421SQE	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS32ELX0421SQX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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