Features • 5-bit DDR LVDS parallel data interface • Programmable Receive Equalization • Selectable DC-balance decoder • Selectable De-scrambler • Remote Sense for automatic detection and negotiation of link status • No external receiver reference clock required • LVDS parallel interface • Programmable LVDS output clock delay • Supports output data-valid signaling • Supports keep-alive clock output • On chip LC VCOs • Redundant serial input (ELX device only) • Retimed serial output (ELX device only) • Configurable PLL loop bandwidth • Configurable via SMBus • Loss of lock and error reporting • 48-pin LLP package with exposed DAP Description The DS32EL0124/ DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface. The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs. The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path. The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins. Key Specification • 1.25 to 3.125 Gbps serial data rate • 125 to 312.5 MHz DDR parallel clock • -40° to +85°C temperature range • > 8 kV ESD (HBM) protection • 0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps) Applications • Imaging: Industrial, Medical Security, Printers • Displays: LED walls, Commercial • Video Transport • Communication Systems • Test and Measurement • Industrial Bus

Also Recommended DS32ELX0421▲ Matching 3.125 Gbps Serializer With 5-bit DDR LVDS Interface Typ App Diagram MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application click for larger image Typ App Diagram	Connection Diagram click for larger image EL Pin Diagram
Typical Performance click for larger image Typ Perf CLK_40mCat5e_1.25G

Datasheet

Title		Size	Date	Other Language
	DS32EL0124 , DS32ELX0124 125 MHz — 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface	1563 Kbytes	9-Nov-09

Featured Application Notes

Title		Size	Date	Other Language
	AN-1979: Application Note 1979 LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers	146 Kbytes	2-Jul-09
	AN-1887: Application Note 1887 Expanding the Payload with National’s FPGA-Link DS32ELX0421 and DS32ELX0124 Serializer and Deserializer	122 Kbytes	12-Sep-08

More Application Notes

Title		Size	Date	Other Language
	AN-903: Application Note 903 A Comparison of Differential Termination Techniques	196 Kbytes	2-Oct-02
	AN-967: Application Note 967 LocalTalk Physical Layer Alternatives	58 Kbytes	5-Oct-98

Design Tools

Title	Size	Date
Interfacing National's FPGA-Link Ser/Des with Altera Cyclone III FPGAs	135 Kbytes	21-Jul-2009
Article - FPGA-Link SerDes Reference Design

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS32ELX0124SQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS32ELX0124SQE	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS32ELX0124SQX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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