DS32EL0124 - 125 - 312.5 MHz Deserializer with DDR LVDS Parallel Interface

Datasheet	Packaging	Samples & Pricing	Reliability	Design Tools	Knowledge Base

Features

•	5-bit DDR LVDS parallel data interface
•	Programmable Receive Equalization
•	Selectable DC-balance decoder
•	Selectable De-scrambler
•	Remote Sense for automatic detection and negotiation of link status
•	No external receiver reference clock required
•	LVDS parallel interface
•	Programmable LVDS output clock delay
•	Supports output data-valid signaling
•	Supports keep-alive clock output
•	On chip LC VCOs
•	Redundant serial input (ELX device only)
•	Retimed serial output (ELX device only)
•	Configurable PLL loop bandwidth
•	Configurable via SMBus
•	Loss of lock and error reporting
•	48-pin LLP package with exposed DAP

Key Specification

•	1.25 to 3.125 Gbps serial data rate
•	125 to 312.5 MHz DDR parallel clock
•	-40° to +85°C temperature range
•	> 8 kV ESD (HBM) protection
•	0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)

General Description

The DS32EL0124/ DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. More...

Applications

•	Imaging: Industrial, Medical Security, Printers
•	Displays: LED walls, Commercial
•	Video Transport
•	Communication Systems
•	Test and Measurement
•	Industrial Bus

Typical Application

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Typ App Diagram

Parameters Values

Function Deserializer

Total Throughput 3125 Mbps

Payload/Channel 3125 Mbps

Signal Conditioning Equalizer

Clock Min 125 MHz

Clock Max 312.5 MHz

Input Compatibility CML

Output Compatibility LVDS

Reference Clock Req'd Deserializer No

Reach 20 meters CAT6

Other Supply 2.5

SupplyVoltage 3.3 Volt

ESD 8 kV

Temperature Min -40 deg C

Temperature Max 85 deg C

Compression Ratio 5:1 DDR

Parallel Bus Width 5 bits

Number Receivers 1

Communications Yes

Sensing & Imaging Yes

Typical Performance

click for larger image

Typ Perf CLK_40mCat5e_1.25G

Also Recommended

DS32EL0421▲	Matching 3.125 Gbps Serializer With 5-bit DDR LVDS Interface
DS32ELX0124▲	Reclocking 3.125 Gbps DeSerializer With Active Loop-through Output For Daisy Chaining

Additional Resources

Design Tools

Connection Diagram

click for larger image

EL Pin Diagram

Datasheet

RoHS Compliance Information	Size in Kbytes	Date
DS32EL0124 , DS32ELX0124 125 MHz — 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface	1563 Kbytes	4-Jun-09	Download

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Package Availability, Models, Samples & Pricing

Part Number

Package

Factory Lead Time

Models

Samples &
Electronic
Orders

Budgetary Pricing

Std
Pack
Size

Package
Marking
Format

Type

Pins

Spec.

MSL
Rating

Peak
Reflow

RoHS
Report

CAD
Symbols

Weeks

Qty

$US each

DS32EL0124SQE

LLP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$10.00

reel
of
250

NS
UZXYTTE#
32EL0124

6 weeks

N/A

DS32EL0124SQ

LLP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$10.00

reel
of
1000

NS
UZXYTTE#
32EL0124

6 weeks

N/A

DS32EL0124SQX

LLP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$10.00

reel
of
2500

NS
UZXYTTE#
32EL0124

6 weeks

N/A

General Description

The DS32EL0124/ DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.

The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.

The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.

The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.

Reliability Metrics

Part Number	Process	EFR Sample Size	LTA Device Hours	FITS	MTTF (Hours)
DS32EL0124SQ	BICMOS8B+	1152	743900	5	211083656
DS32EL0124SQE	BICMOS8B+	1152	743900	5	211083656
DS32EL0124SQX	BICMOS8B+	1152	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Design Tools

Title	Size in Kbytes	Date
Interfacing National's FPGA-Link Ser/Des with Altera Cyclone III FPGAs	135 Kbytes	21-Jul-2009	View Online	Download
Article - High-Performance SerDes Module with Easy FPGA Interface and Cable Detect			View

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Application Notes

Title	Size in Kbytes	Date
AN-1979: Application Note 1979 LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers	146 Kbytes	2-Jul-09	Download

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[Information as of 7-Nov-2009]