Features • AECQ-100 Grade 3 • DC - 3.125 Gbps low jitter, low skew, low power operation • Pin configurable, fully differential, non-blocking architecture • On-chip 100Ω input and output terminations minimize return losses, reduce component count and minimize board space • 8 kV ESD on LVDS I/O pins protects adjoining components • Small 4 mm x 4 mm LLP-16 space saving package Description The DS25CP152Q is a 3.125 Gbps 2x2 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture allows connections of any input to any output or outputs. Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower device return losses, reduce component count and further minimize board space. Applications • Automotive display applications • Clock and data buffering and muxing • OC-48 / STM-16 • SD/HD/3G HD SDI Routers

Also Recommended DS10CP152Q▲ DC To 1.5 Gbps 2 X 2 Crosspoint DS25CP102Q▲ 3.125 Gbps 2 X 2 Crosspoint With Equalization And Pre-emphasis DS25CP152▲ DS25CP152EVK Eval Kit MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application click for larger image	Block Diagram click for larger image
Typical Performance click for larger image

Datasheet

Title		Size	Date	Other Language
	DS25CP152Q Automotive 3.125 Gbps LVDS 2x2 Crosspoint Switch	284 Kbytes	5-Mar-09

Featured Application Notes

Title		Size	Date	Other Language
	AN-1957: Application Note 1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter	1049 Kbytes	23-Apr-09

More Application Notes

Title		Size	Date	Other Language
	AN-1971: Application Note 1971 Triple Rate SDI IP FPGA Resource Utilization on the SDXILEVK/AES-EXP-SDI-G Reference Design	195 Kbytes	6-May-09

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS25CP152QSQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS25CP152QSQX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.