Datasheet
RoHS Compliance Information
| Size in Kbytes | Date |
 |
| DS25CP104A / DS25CP114 3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit Pre-Emphasis and Receive Equalization |
582
Kbytes |
13-May-09 |
Download |
Package Availability, Models, Samples & Pricing
General Description
The DS25CP104A and DS25CP114 are 3.125 Gbps 4x4 LVDS crosspoint switches optimized for high-speed signal routing and switching
over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional
signal integrity and noise immunity. The non-blocking architecture allows connections of any input to any output or outputs.
The switch configuration can be accomplished via external pins or the System Management Bus (SMBus) interface.
The DS25CP104A and DS25CP114 feature four levels (Off, Low, Medium, High) of transmit pre-emphasis (PE) and four levels (Off,
Low, Medium, High) of receive equalization (EQ) settable via the SMBus interface. Off and Medium PE levels and Off and Low
EQ levels are settable with the external pins. In addition, the SMBus circuitry enables the loss of signal (
^LOS) monitors that can inform a system of the presence of an open inputs condition (e.g. disconnected cable).
Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are
LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board
layout. On the DS25CP104A each differential input and output is internally terminated with a 100Ω resistor to lower return
losses, reduce component count and further minimize board space. For added design flexibility the 100Ω input terminations
on the DS25CP114 have been eliminated. This enables a designer to build custom crosspoint configurations and distribution
circuits that require a limited multidrop signaling topology.
Reliability Metrics
| Part Number |
Process |
EFR Reject |
EFR Sample Size |
PPM |
LTA Rejects |
LTA Device Hours |
FITS |
MTTF (Hours) |
|
DS25CP104ATSQ | BICMOS8B+ | 0 | 1152 | 0 | 0 | 743900 | 5 | 211083656
|
|
DS25CP104ATSQX | BICMOS8B+ | 0 | 1152 | 0 | 0 | 743900 | 5 | 211083656
|
Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR.
The Long Term Failure Rates were calculated
at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress
temperature of 150°C to an application temperature of 55°C.
For more information on Reliability Metrics, please click here.
Design Tools
| Title | Size in Kbytes |
Date |
|
|
|
| DS25CP104 in 3G SDI Router Application |
737 Kbytes |
27-Aug-2008 |
View Online |
Download |
|
Application Notes
| Title | Size in Kbytes |
Date |
|
| AN-1957: Application Note 1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter |
1049
Kbytes |
23-Apr-09 |
Download |
| AN-1898: Application Note 1898 LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces |
308
Kbytes |
4-Sep-08 |
Download |
More Application Notes
| Title | Size in Kbytes |
Date |
|
| AN-1971: Application Note 1971 Triple Rate SDI IP FPGA Resource Utilization on the SDXILEVK/AES-EXP-SDI-G Reference Design |
195
Kbytes |
6-May-09 |
Download |
[Information as of 8-Nov-2009]
|
