Features • DC - 3.125 Gbps low jitter, low skew, low power operation • Pin configurable, fully differential, non-blocking architecture • Pin selectable transmit pre-emphasis and receive equalization eliminate data dependant jitter • Wide Input Common Mode Voltage Range allows DC-coupled interface to CML and LVPECL drivers • On-chip 100Ω input and output termination minimizes insertion and return losses, reduces component count and minimizes board space • 8 kV ESD on LVDS I/O pins protects adjoining components • Small 4 mm x 4 mm LLP-16 space saving package Description The DS25CP102 is a 3.125 Gbps 2x2 LVDS crosspoint switch optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture allows connections of any input to any output or outputs. The DS25CP102 features two levels (Off and On) of transmit pre-emphasis (PE) and two levels (Off and On) of receive equalization (EQ). Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower device insertion and return losses, reduce component count and further minimize board space. Applications • High-speed channel select applications • Clock and data buffering and muxing • OC-48 / STM-16 • SD/HD/3GHD SDI Routers

MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application click for larger image	Block Diagram click for larger image
Typical Performance *click for larger image

Datasheet

Title		Size	Date	Other Language
	DS25CP102 3.125 Gbps 2X2 LVDS Crosspoint Switch with Transmit Pre-Emphasis and Receive Equalization	398 Kbytes	18-Mar-09

Featured Application Notes

Title		Size	Date	Other Language
	AN-1957: Application Note 1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter	1049 Kbytes	23-Apr-09
	AN-1898: Application Note 1898 LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces	308 Kbytes	4-Sep-08	中文

More Application Notes

Title		Size	Date	Other Language
	AN-1971: Application Note 1971 Triple Rate SDI IP FPGA Resource Utilization on the SDXILEVK/AES-EXP-SDI-G Reference Design	195 Kbytes	6-May-09

Design Tools

Title	Size	Date
3.125 Gbps 2x2 LVDS Crosspoint Switch Evaluation Board

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS25CP102TSQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS25CP102TSQX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.