Features • DC - 3.125 Gbps low jitter, low skew, low power operation • Pin selectable transmit pre-emphasis and receive equalization eliminate data dependant jitter • Wide input common mode voltage range allows DC-coupled interface to LVDS, CML and LVPECL drivers • ^LOS circuitry detects open inputs fault • Integrated 100Ω input and output terminations • 8 kV ESD on LVDS I/O pins protects adjoining components • Small 6 mm x 6 mm LLP-40 space saving package Description The DS25BR440 is a 3.125 Gbps Quad LVDS buffer optimized for high-speed signal routing and repeating over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The DS25BR440 features two levels of transmit pre-emphasis (PE) and two levels of receive equalization (EQ). Both of these features compensate for interconnect losses and ultimately maximize noise margin. A loss-of-signal ( ^LOS) circuit monitors each input channel and a unique ^LOS pin is asserted when no signal is detected at that input Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower device return losses, reduce component count and further minimize board space. Applications • Clock and data buffering and repeating • Copper cable driving and equalization • FR-4 equalization • OC-48 / STM-16

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Typical Application *click for larger image	Block Diagram *click for larger image
Typical Performance *click for larger image Equalization with 20 and 40 inch striplines

Datasheet

Title		Size	Date	Other Language
	DS25BR440 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization	357 Kbytes	11-Feb-08

Featured Application Notes

Title		Size	Date	Other Language
	AN-1957: Application Note 1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter	1049 Kbytes	23-Apr-09

More Application Notes

Title		Size	Date	Other Language
	AN-1898: Application Note 1898 LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces	308 Kbytes	4-Sep-08	中文

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS25BR440TSQ	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS25BR440TSQX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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