Features • DC - 3.125 Gbps low jitter, high noise immunity, low power operation • Receive equalization reduces ISI jitter due to media loss • Transmit pre-emphasis drives lossy backplanes and cables • On-chip 100Ω input and output termination minimizes insertion and return losses, reduces component count and minimizes board space. The DS25BR101 eliminates the on-chip input termination for added design flexibility. • 7 kV ESD on LVDS I/O pins protects adjoining components • Small 3 mm x 3 mm LLP-8 space saving package Description The DS25BR100 and DS25BR101 are single channel 3.125 Gbps LVDS buffers optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The DS25BR100 and DS25BR101 feature transmit pre-emphasis (PE) and receive equalization (EQ), making them ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization. Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. On the DS25BR100 the differential input and output is internally terminated with a 100Ω resistor to lower return losses, reduce component count and further minimize board space. For added design flexibility the 100Ω input terminations on the DS25BR101 have been eliminated. This enables a designer to adjust the termination for custom interconnect topologies and layout. Applications • Clock and data buffering • Metallic cable driving and equalization • FR-4 equalization

Also Recommended DS25BR110▲ Additional Levels Of Equalization DS25BR120▲ Additional Levels Of Pre-Emphasis DS25BR150▲ 3.125Gbps LVDS Buffer MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application click for larger image	Block Diagram click for larger image

Datasheet

Title		Size	Date	Other Language
	DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization	478 Kbytes	11-Aug-09	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1898: Application Note 1898 LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces	308 Kbytes	4-Sep-08	中文
	AN-1957: Application Note 1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter	1049 Kbytes	23-Apr-09

More Application Notes

Title		Size	Date	Other Language
	AN-1613: Application Note 1613 Extending HDMI Cable Reach Using National`s DS16EV5110A, DS22EV5110 and DS34RT5110 Equalizers	8538 Kbytes	16-Oct-09	中文

Design Tools

Title	Size	Date
DS25BR100EVK Evaluation Board Design Documentation

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS25BR100TSD	BICMOS8B+	0	1152	0	0	743900	5	211083656
DS25BR100TSDX	BICMOS8B+	0	1152	0	0	743900	5	211083656

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.