ADC16V130 - 16-Bit, 130 MSPS A/D Converter with LVDS Outputs from the PowerWise® Family

Datasheet Packaging Samples & Pricing Eval. Boards Reference Designs Knowledge Base

Features
•Dual Supplies: 1.8V and 3.0V operation
•On chip automatic calibration during power-up
•Low power consumption
•Multi-level multi-function pins for CLK/DF and PD
•Power-down and sleep modes
•On chip precision reference and sample-and-hold circuit
•On chip low jitter duty-cycle stabilizer
•Offset binary or 2's complement data format
•Full data rate LVDS output port
•64-pin LLP package (9x9x0.8, 0.5mm pin-pitch)

Key Specification

Resolution

16 Bits

Conversion Rate

130 MSPS

SNR

  (fIN = 10MHz)

  (fIN = 70MHz)

  (fIN = 160MHz)

  

78.5 dBFS (typ)

77.8 dBFS (typ)

76.7 dBFS (typ)

SFDR

  (fIN = 10 MHz)

  (fIN = 70MHz)

  (fIN = 160MHz)

  

95.5 dBFS (typ)

92.0 dBFS (typ)

90.6 dBFS (typ)

Full Power Bandwidth

1.4 GHz (typ)

Power Consumption

 Core

 LVDS Driver

 Total

  

650 mW (typ)

105 mW (typ)

755 mW (typ)

 Operating Temperature Range

-40°C ~ 85°C

General Description

The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). More...


Applications


•High IF Sampling Receivers
•Multi-carrier Base Station Receivers
•GSM/EDGE, CDMA2000, UMTS, LTE and WiMax
•Test and Measurement Equipment
•Communications Instrumentation
•Data Acquisition
•Portable Instrumentation
  Typical Application
*click for larger image


Parametric Table     expand
Parametric Table    collapse
Resolution 16 bits
Channels 1 Channels
SNR 78.5 dB
SFDR 95.5 dB
ENOB 12.7 bits
Max Sample Rate 130 MSPS
Min Sample Rate 20 MSPS
Power Dissipation 0.755 Watt
PowerWise Rating 1 0.87 pJ/conv
Resolution 16 bits
Channels 1 Channels
SNR 78.5 dB
SFDR 95.5 dB
ENOB 12.7 bits
Max Sample Rate 130 MSPS
Min Sample Rate 20 MSPS
Power Dissipation 0.755 Watt
PowerWise Rating 1 0.87 pJ/conv
INL (+/-) 1.5 LSB
SINAD 78.3 dB
DNL (+/-) 0.45 LSB
THD dB -91.5 dB
Min Supply Voltage 2.7 Volt
Max Supply Voltage 3.6 Volt
Nominal Vin 2.4 Vpp
Temperature Min -40 deg C
Temperature Max 85 deg C
Data Converter Type ADC
PowerWise Yes
View Using Catalog


Typical Performance

*click for larger image


  Also Recommended
LMH6517Low-distortion, High-bandwidth Driver

Additional Resources

Online Seminars
Block Diagram
click for larger image

Block Diagram

Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
ADC16V130 16-Bit, 130 MSPS A/D Converter with LVDS Outputs 572 Kbytes 8-Apr-09 Download

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Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders		Budgetary PricingStd
Pack
Size		Package
Marking
Format
TypePinsSpec.MSL
Rating		Peak
Reflow		RoHS
Report		CAD
Symbols		WeeksQtyQty$US each
SP16130CH4RBLow IF Receiver Reference DesignFull productionN/A
 
Buy Now 		 CALLN/A-
N/AN/A
ADC16V130EB16-Bit, 130 MSPS A/D Converter with LVDS Outputs Evaluation BoardFull productionN/A
 
Buy Now 		1+$702.001-
N/AN/A
ADC16V130CISQLLP64NOPB3260RoHS N/A Full productionN/A
Samples
Buy Now 		1K+$69.00reel
of
250		NS
UZXYTT
ADC16V130
16 weeksN/A
ADC16V130CISQELLP64NOPB3260RoHS N/A Full productionN/A
 
Buy Now 		1K+$69.00reel
of
250		NS
UZXYTT
ADC16V130
16 weeksN/A
ADC16V130CISQXLLP64NOPB3260RoHS N/A Full productionN/A
 
Buy Now 		1K+$69.00reel
of
2000		NS
UZXYTT
ADC16V130
16 weeksN/A

General Description

The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising its dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The digital data is provided via full data rate LVDS outputs – making possible the 64-pin, 9mm x 9mm LLP package. The ADC16V130 operates on dual power supplies +1.8V and +3.0V with a power-down feature to reduce the power consumption to very low levels while allowing fast recovery to full operation.


Reference Designs
•RD-170 - Low IF Receiver Reference Design

[Information as of 3-Jul-2009]