ADC14V155 - 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs from the PowerWise® Family

Datasheet Packaging Samples & Pricing Eval. Boards Design Tools Reference Designs Knowledge Base

Features
1.1 GHz Full Power Bandwidth
Internal sample-and-hold circuit
Low power consumption
Internal precision 1.0V reference
Single-ended or Differential clock modes
Clock Duty Cycle Stabilizer
Dual +3.3V and +1.8V supply operation
Power-down and Sleep modes
Offset binary or 2's complement output data format
Dual Data Rate (DDR) LVDS outputs
Pin-compatible: ADC12V170
48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)

Key Specification


Resolution

14 Bits

Conversion Rate

155 MSPS

SNR (fIN = 70 MHz)

71.7 dBFS (typ)

SFDR (fIN = 70 MHz)

86.9 dBFS (typ)

ENOB (fIN = 70 MHz)

11.5 bits (typ)

Full Power Bandwidth

1.1 GHz (typ)

Power Consumption

951 mW (typ)

General Description


The ADC14V155 is a high-performance CMOS analog-to-digital converter with LVDS outputs. More...


Applications


High IF Sampling Receivers
Wireless Base Station Receivers
Power Amplifier Linearization
Multi-carrier, Multi-mode Receivers
Test and Measurement Equipment
Communications Instrumentation
Radar Systems
  Typical Application
*click for larger image

application circuit

Parametric Table     expand
Parametric Table    collapse
Resolution 14 bit
Channels 1 Channels
SNR 71.7 dB
SFDR 86.9 dB
ENOB 11.5 bit
Max Sample Rate 155 MSPS
Min Sample Rate 5 MSPS
Power Dissipation 0.951 Watt
PowerWise Rating 1 2.12 pJ/conv
Resolution 14 bit
Channels 1 Channels
SNR 71.7 dB
SFDR 86.9 dB
ENOB 11.5 bit
Max Sample Rate 155 MSPS
Min Sample Rate 5 MSPS
Power Dissipation 0.951 Watt
PowerWise Rating 1 2.12 pJ/conv
INL (+/-) 2.4 LSB
SINAD 71.2 dB
DNL (+/-) 0.55 LSB
THD dB -82.2 dB
Min Supply Voltage 3 Volt
Max Supply Voltage 3.6 Volt
Nominal Vin 2 Vpp
Temperature Min -40 deg C
Temperature Max 85 deg C
Data Converter Type ADC
PowerWise Yes
View Using Catalog


Typical Performance


*click for larger image

noise vs. fin
  Also Recommended
ADC14155CMOS Output Version Of The ADC14V155
LMH6552Low-distortion, High-bandwidth Driver

Additional Resources


Design Tools (see below)


Block Diagram


*click for larger image

block diagram

Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
ADC14V155 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs 434 Kbytes 23-May-08 View Online
Download
ADC14V155 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs (Japanese)
701 Kbytes   Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.


Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
Format
TypePinsSpec.MSL
Rating
Peak
Reflow
RoHS
Report
CAD
Symbols
WeeksQtyQty$US each
ADC14V155HFEBADC14V155 evaluation board for input frequencies greater than 150 MHzFull productionN/A
 
Buy Now
1+$495.001-
8 weeksN/A
ADC14V155KDRBHigh IF Sampling Receiver System Reference DesignFull productionN/A
 
Buy Now
1+$800.001-
8 weeksN/A
ADC14V155LFEBADC14V155 evaluation board for input frequencies less than 150 MHzFull productionN/A
 
Buy Now
1+$495.001-
8 weeksN/A
ADC14V155CISQLLP48STD
NOPB
3
3
260
260
RoHS N/A Full productionN/A
Samples
Buy Now
25+$85.80reel
of
250
NS
UZXYTT
14V155SQ
6 weeks100

Obsolete Parts

Obsolete PartAlternate Part or SupplierSourceLast Time Buy Date
ADC14V155CISQE
ADC14V155CISQ
NONE
05/29/2008

General Description


The ADC14V155 is a high-performance CMOS analog-to-digital converter with LVDS outputs. It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14V155 operates from dual +3.3V and +1.8V power supplies and consumes 951 mW of power at 155 MSPS.

The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 15 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.

The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14V155 can be operated with an external reference.

Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.

The ADC14V155 is pin-compatible with the ADC12V170. It is available in a 48-lead LLP package and operates over the industrial temperature range of −40°C to +85°C.

Design Tools


TitleSize in Kbytes Date Click link below to Download    
Evaluation Systems 32 Kbytes 2-Jun-2008 View    

If you have trouble printing or viewing PDF file(s), see Printing Problems.


Reference Designs
RD-146 - High IF Receiver Reference Design

Application Notes


TitleSize in Kbytes Date Click link below to Download
AN-1721: Application Note 1721 High Speed ADCs with Interfacing, Driving and Clocking Schemes 186 Kbytes 20-Sep-07 Download
AN-1721 (Japanese): Application Note 1721 High Speed ADCs with Interfacing, Driving and Clocking Schemes
256 Kbytes   Download
AN-1721 (Chinese): Application Note 1721 High Speed ADCs with Interfacing, Driving and Clocking Schemes
399 Kbytes  

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 21-Nov-2008]