RoHS Compliance Information	Size in Kbytes	Date
ADC14V155 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs	434 Kbytes	23-May-08	View Online Download
ADC14V155 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs (Japanese)	701 Kbytes

Part Number

Package

Factory Lead Time

Models

Samples & Electronic Orders

Budgetary Pricing

Std Pack Size

Package Marking Format

Type

Pins

Spec.

MSL Rating

Peak Reflow

RoHS Report

CAD Symbols

Weeks

Qty

Qty

$US each

ADC14V155HFEB

ADC14V155 evaluation board for input frequencies greater than 150 MHz

Full production

N/A

1+

$495.00

1

-

8 weeks

N/A

ADC14V155KDRB

High IF Sampling Receiver System Reference Design

Full production

N/A

1+

$800.00

1

-

8 weeks

N/A

ADC14V155LFEB

ADC14V155 evaluation board for input frequencies less than 150 MHz

Full production

N/A

1+

$495.00

1

-

8 weeks

N/A

ADC14V155CISQ

LLP

48

STD NOPB

3 3

260 260

RoHS

N/A

Full production

N/A

25+

$85.80

reel of 250

NS UZXYTT 14V155SQ

6 weeks

100

Obsolete Parts

General Description

The ADC14V155 is a high-performance CMOS analog-to-digital converter with LVDS outputs. It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14V155 operates from dual +3.3V and +1.8V power supplies and consumes 951 mW of power at 155 MSPS.

The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 15 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.

The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14V155 can be operated with an external reference.

Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.

The ADC14V155 is pin-compatible with the ADC12V170. It is available in a 48-lead LLP package and operates over the industrial temperature range of −40°C to +85°C.

Design Tools

Title	Size in Kbytes	Date
Evaluation Systems	32 Kbytes	2-Jun-2008	View

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Application Notes

Title	Size in Kbytes	Date
AN-1721: Application Note 1721 High Speed ADCs with Interfacing, Driving and Clocking Schemes	186 Kbytes	20-Sep-07	Download
AN-1721 (Japanese): Application Note 1721 High Speed ADCs with Interfacing, Driving and Clocking Schemes	256 Kbytes
AN-1721 (Chinese): Application Note 1721 High Speed ADCs with Interfacing, Driving and Clocking Schemes	399 Kbytes