Features • Internal sample-and-hold circuit and precision reference • Low power consumption • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V supply operation • Power-down mode • Offset binary or 2's complement output data format • 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch) Description The ADC14DC105 is a high-performance CMOS analog-to-digital converter capable of converting two analog input signals into 14-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC14DC105 may be operated from a single +3.0 V or +3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14DC105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC14DC105 is available in a 60-lead LLP package and operates over the industrial temperature range of −40°C to +85°C. Key Specification Resolution 14 Bits Conversion Rate 105 MSPS SNR (fIN = 170 MHz) 71 dBFS (typ) SFDR (fIN = 170 MHz) 83 dBFS (typ) Full Power Bandwidth 1 GHz (typ) Power Consumption 690 mW (typ), VA=3.0V 800 mW (typ), VA=3.3V Applications • High IF Sampling Receivers • Wireless Base Station Receivers • Test and Measurement Equipment • Communications Instrumentation • Portable Instrumentation

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Typical Application click for larger image Application Circuit	Block Diagram click for larger image Block Diagram
Typical Performance *click for larger image SNR and SFDR vs Fin

Datasheet

Title		Size	Date	Other Language
	ADC14DC105 Dual 14-Bit, 105 MSPS A/D Converter with CMOS Outputs	432 Kbytes	23-Oct-08	日本語

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