Low power consumption, further reduced at lower Fs
Internally terminated, buffered, differential analog inputs
R/W SPI Interface for Extended Control Mode
Dual-Edge Sampling Mode, in which the I- and Q-channels sample one input at twice the sampling clock rate
Test patterns at output for system debug
Programmable 15-bit gain and 12-bit plus sign offset
Programmable tAD adjust feature
1:1 non-demuxed or 1:2 demuxed LVDS outputs
AutoSync feature for multi-chip systems
Single 1.9V ± 0.1V power supply
292-ball BGA package (27mm x 27mm x 2.4mm with 1.27mm ball-pitch); no heat sink required
Description
The ADC10D1000/1500 is the latest advance in National's Ultra-High-Speed ADC family. This low-power, high-performance CMOS
analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS
(Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and
dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball
thermally enhanced BGA package over the rated industrial temperature range of
-40°C to +85°C.
The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded
feature set includes AutoSync for multi-chip synchronization,
15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold
amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing
9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10
-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply,
this device is guaranteed to have no missing codes over the full operating temperature range.
Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up,
so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock.
If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate
is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS
ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and
the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of
an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.
The ADC10D1000 is the latest advance in National?s Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0 GSPS (Non-DES Mode) or for a single channel up to 2.0 GSPS (DES Mode). The ADC10D1000 achieves excellent accuracy and dynamic performance while dissipating less than 2.8 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package which does not require a head sink over the rated industrial temperature range of -40°C to 85°C.
The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.0 Effective Number of Bits (ENOB) with a 498 MHz input signal and a 1.0 GHz sample rate while providing a 10-18 Code Error Rate (CER). Dissipating a typical 2.77 Watts in Non-Demultiplex Mode at 1.0 GSPS from a single 1.9V supply, this device is guaranteed to have no missing codes over the full operating temperature range.
Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two`s complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1966, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.
If the ADC is being used in DESIQ Mode, a DESIQ Balun Board is available to drive the ADC externally.
Features:
Excellent accuracy and dynamic performance
Low power consumption, further reduced at lower Fs
Internally terminated, buffered, differential analog inputs
R/W SPI interface for Extended Control Mode
Dual-Edge Sampling Mode, in which the I- and Q-channels sample one input at twice the sampling clock rate
Test patterns at output for system debug
Programmable 15-bit gain and 12-bit plus sign offset
Programmable tAD adjust feature
1:1 non-demuxed or 1:2 demuxed LVDS outputs
AutoSync feature for multi-chip systems
Single 1.9V ± 0.1V power supply
292-ball BGA package (27mm x 27mm x 2.4mm with 1.27mm ball-patch); no heat sink required
The TC1 DESIQ Single Balun Board is an accessory board which is designed to drive the ADC1xD1x00RB in DESIQ Mode. It takes a single-ended signal (SMA input) and can drive the I+, I-, Q+ and Q- inputs to the Gig ADC Reference Board.
This board has the Mini-Circuits TC1-1-13MA+ balun on it, which rated performance is from 4.5 MHz to 3000 MHz.
Please note that this board cannot be used to drive the DESCLKIQ Mode. This is because the DESCLKIQ Mode requires I- and Q-channel inputs to be balanced more precisely than can be achieved by two separate boards attached by cables. Using this board to drive the DESCLKIQ Mode is functionally possible, but there will be a large interleaving spur, which cannot be minimized to achieve reasonable SFDR performance.
National Semiconductor follows the provisions of the Product Stewardship Guide for Customers
(CSP-9-111C1)
and Banned Substances and Materials of Interest Specification
(CSP-9-111S2)
for regulatory environmental compliance. Details may be found at:
www.national.com/en/packaging/greennopb.html.
Lead free products are RoHS compliant.
Lead Free product status is available through the search tool located
here
Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR.
The Long Term Failure Rates were calculated
at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress
temperature of 150°C to an application temperature of 55°C.
For more information on Reliability Metrics, please click here.
ADC08D1020
