RoHS Compliance Information	Size in Kbytes	Date
ADC08D1000 High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter	1280 Kbytes	20-Mar-08	View Online	Download	Receive via Email
ADC08D1000 High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter (Japanese)	1341 Kbytes
ADC08D1000QML High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter	1310 Kbytes	9-May-07	View Online	Download	Receive via Email

Part Number

Package

Factory Lead Time

Models

Samples & Electronic Orders

Budgetary Pricing

Std Pack Size

Package Marking Format

Type

Pins

Spec.

MSL Rating

Peak Reflow

RoHS Report

CAD Symbols

Weeks

Qty

Qty

$US each

ADC08D1000DEV

High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter

Full production

N/A

1+

$3500.00

1

-

8 weeks

N/A

ADC08D1000EVAL

High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter

Full production

N/A

1+

$2400.00

1

-

8 weeks

N/A

ADC08D1000CIYB

LQFP EXP PAD

128

STD NOPB

3 3

260 260

RoHS

Download

Full production

adc08d1000.ibs

25+

$304.00

tray of 60

NSUZXYYTTE# ADC08D1000 CIYB

6 weeks

100

ADC08D1000WG-QV

CQGP

128

STD

1

260

RoHS

Download

Full production

N/A

CALL

tray of N/A

NSZSSXXYYA ADC08D1000 WG-QV 5962- 0520601VZC Q

N/A

N/A

ADC08D1000WGFQV

CQGP

128

STD

1

260

RoHS

Download

Full production

N/A

CALL

tray of N/A

NSZSSXXYYA ADC08D1000 WGFQV 5962F 0520601VZC Q

N/A

N/A

General Description

The ADC08D1000 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.3 GSPS. Consuming a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.4 ENOB with a 500 MHz input signal and a 1 GHz sample rate while providing a 10 -18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 2 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C ≤ T_A ≤ +85°C) temperature range.

Reliability Metrics

Design Tools

Title	Size in Kbytes	Date
Evaluation Systems	17 Kbytes	29-May-2008	View
National GHz ADC Development Platform for Xilinx FPGAs	6 Kbytes	5-Feb-2008	View

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[Information as of 8-Aug-2008]