RoHS Compliance Information	Size in Kbytes	Date
CLC5903 Dual Digital Tuner/AGC	698 Kbytes	9-Jun-04	Download

Part Number

Package

Factory Lead Time

Models

Samples & Electronic Orders

Budgetary Pricing

Std Pack Size

Package Marking Format

Type

Pins

Spec.

MSL Rating

Peak Reflow

RoHS Report

CAD Symbols

Weeks

Qty

Qty

$US each

CLC5903SM

FBGA

128

NOPB STD

3 3

260 235

RoHS

N/A

Full production

N/A

1K+

$19.00

tray of 168

NSUZXYYTTE# CLC5903SM

8 weeks

10

CLC5903CISM

FBGA

128

NOPB

3

260

RoHS

N/A

Full production

N/A

1K+

$19.00

tray of 168

NSUZXYTTE# CLC5903 CISM

8 weeks

N/A

CLC5903VLA

PQFP

128

NOPB STD

3 3

245 245

RoHS

N/A

Full production

N/A

1K+

$19.00

tray of 66

NSUZXYYTTE# CLC5903VLA

6 weeks

1000

General Description

The CLC5903 Dual Digital Tuner / AGC IC is a two channel digital downconverter (DDC) with integrated automatic gain control (AGC). The CLC5903 is a key component in the Enhanced Diversity Receiver Chipset (EDRCS) which includes one CLC5903 Dual Digital Tuner / AGC, two CLC5957 12-bit analog-to-digital converters (ADCs), and two CLC5526 digitally controlled variable gain amplifiers (DVGAs). This system allows direct IF sampling of signals up to 300MHz for enhanced receiver performance and reduced system costs.

The CLC5903 is an enhanced replacement for the CLC5902 in the Diversity Receiver Chipset (DRCS). The main improvements relative to the CLC5902 are a 50% increase in maximum sample rate from 52MHz to 78MHz, a 62% reduction in power consumption from 760mW to 290mW, and the added flexibility to independently program filter coefficients in the two channels.

The CLC5903 offers high dynamic range digital tuning and filtering based on hard-wired digital signal processing (DSP) technology. Each channel has independent tuning, phase offset, filter coefficients, and gain settings. Channel filtering is performed by a series of three filters. The first is a 4-stage Cascaded Integrator Comb (CIC) filter with a programmable decimation ratio from 8 to 2048. Next there are two symmetric FIR filters, a 21-tap and a 63-tap, both with independent programmable coefficients. The first FIR filter decimates the data by 2, the second FIR decimates by either 2 or 4. Channel filter bandwidth at 52MSPS ranges from ±650kHz down to ±1.3kHz. At 78MSPS, the maximum bandwidth increases to ±975kHz.

The CLC5903’s AGC controller monitors the ADC output and controls the ADC input signal level by adjusting the DVGA setting. AGC threshold, deadband+hysteresis, and the loop time constant are user defined. Total dynamic range of greater than 120dB full-scale signal to noise in a 200kHz bandwidth can be achieved with the Diversity Receiver Chipset.

Reliability Metrics