On chip precision reference and sample-and-hold circuit
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On chip low jitter duty-cycle stabilizer
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Offset binary or 2's complement data format
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Full data rate LVDS output port
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64-pin LLP package (9x9x0.8, 0.5mm pin-pitch)
Description
The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals
into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined
architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external
component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance
and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting
power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board
level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising
its dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The digital data is provided
via full data rate LVDS outputs – making possible the 64-pin, 9mm x 9mm LLP package. The ADC16V130 operates on dual power
supplies +1.8V and +3.0V with a power-down feature to reduce the power consumption to very low levels while allowing fast
recovery to full operation.
The SP16130CH4RB Reference Board demonstrates a low IF receiver subsystem application including an ADC16V130 analog-to-digital converter (ADC) and LMK04031B clock conditioner which provides digitization and clocking as used in wireless infrastructure systems.
This subsystem reference design provides single to differential conversion and lowpass filtering of the input signal with an optimized, double-balun network and high dynamic range digitization to parallel LVDS outputs using the ADC16V130. The 125 MHz low-jitter, LVPECL clock signal for the ADC is generated by a LMK04031B clock conditioner which demonstrates less than 250 fs of total jitter over the input bandwidth of the ADC.
The SP16130CH4RB is factory configured for evaluation of input signals between 5 MHz and 52 MHz. Each board is populated with an analog input network which has a cascade of baluns for single-ended to differential conversion, and a filtering network optimized for these frequencies.
Evaluation of this reference board is simplified with the WaveVision 5.1 Data Capture Board and WaveVision 5 software.
This Design Kit is designed to ease evaluation and design-in of National Semiconductor`s ADC16V130 16-bit Analog-to-Digital Converter with LVDS outputs, which operates at speeds up 130 Msps.
The evaluation board can be used by connecting the board to the WaveVision 5.0 Data Capture Board (order number WAVEVSNBRD5.0), which is connected to a personal computer through a USB port and running WaveVision software, operating under Microsoft Windows. The software can perform an FFT on the captured data upon command and, in addition to a frequency domain plot, shows dynamic performance in the form of SNR, SINAD, THD, SFDR and ENOB.
ADC16V130
