Features • Low power consumption • On-chip precision reference and sample-and-hold circuit • On-chip automatic calibration during power-up • Dual data rate LVDS output port • Dual Supplies: 1.8V and 3.0V operation • Selectable input range: 2.4, 2.0, 1.5 and 1.0VPP • Sampling edge flipping with clock divider by 2 option • Integer clock divider by 1 or 2 • On-chip low jitter duty-cycle stabilizer • Power-down and sleep modes • Output fixed pattern generation • Output clock position adjustment • 3-wire SPI • Offset binary or 2's complement data format • 68-pin LLP package (10x10x0.8, 0.5mm pin-pitch) Description The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 160 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16DV160 can be re-calibrated at any time through the 3-wire Serial Peripheral Interface (SPI). An integrated low noise and stable voltage reference and differential reference buffer amplifier eases board level design. The on-chip duty cycle stabilizer with low additive jitter allows a wide range of input clock duty cycles without compromising dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver block can be easily verified and optimized via fixed pattern generation and output clock position features. The digital data is provided via dual data rate LVDS outputs – making possible the 68-pin, 10 mm x 10 mm LLP package. The ADC16DV160 operates on dual power supplies of +1.8V and +3.0V with a power-down feature to reduce power consumption to very low levels while allowing fast recovery to full operation. Key Specification Resolution 16 Bits Conversion Rate 160 MSPS SNR   (@FIN = 30 MHz)   (@FIN = 197 MHz)    78.5 dBFS (typ) 76.3 dBFS (typ) SFDR   (@FIN = 30 MHz)   (@FIN = 197 MHz)    95 dBFS (typ) 91.2 dBFS (typ) Full Power Bandwidth 1.4 GHz (typ) Power Consumption  -Core per channel  -LVDS Driver  -Total    591 mW (typ) 118 mW (typ) 1.3W (typ)  Operating Temperature Range -40°C ~ 85°C Applications • Multi-carrier, Multi-standard Base Station Receivers • -MC-GSM/EDGE, CDMA2000, UMTS, LTE and WiMAX • High IF Sampling Receivers • Diversity Channel Receivers • Test and Measurement Equipment • Communications Instrumentation • Portable Instrumentation

Also Recommended ADC16V130▲ High-performance Single-channel 16-bit, 130-MSPS ADC LMH6517 High-performance, High-speed DVGA LMH6554 High-speed, High-performance Differential Driver LMK04000 Precision Clock Conditioner With Dual PLL transformer drive circ. for high input freq. MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

Typical Application *click for larger image transformer drive circ. for high input freq.	Block Diagram click for larger image Functional Block Diagram

Datasheet

Title		Size	Date	Other Language
	ADC16DV160 Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs	694 Kbytes	17-Aug-09

Featured Application Notes

Title		Size	Date	Other Language

More Application Notes

Title		Size	Date	Other Language
	AN-1261: Application Note 1261 Power Supply Effects on Noise Performance	78 Kbytes	16-Mar-07	中文

Design Tools

Reference Design

RD-179 - High-IF Sub-sampling Receiver Subsystem

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
ADC16DV160CILQ	CMOS9	1	7327	137	0	1103000	4	312979261
ADC16DV160CILQE	CMOS9	1	7327	137	0	1103000	4	312979261
ADC16DV160CILQX	CMOS9	1	7327	137	0	1103000	4	312979261

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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