ADC14DS080 - Dual 14-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs from the PowerWise® Family
Datasheet Packaging Samples & Pricing Eval. Boards Design Tools Knowledge Base

Features
Clock Duty Cycle Stabilizer
Single +3.0V or 3.3V supply operation
Serial LVDS Outputs
Serial Control Interface
Overrange outputs
60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)

Key Specification


Resolution

14 Bits

Conversion Rate

80 MSPS

SNR (fIN = 170 MHz)

72 dBFS (typ)

SFDR (fIN = 170 MHz)

82 dBFS (typ)

Full Power Bandwidth

1 GHz (typ)

Power Consumption

800 mW (typ)

General Description


The ADC14DS080 is a high-performance CMOS analog-to-digital converter capable of converting two analog input signals into 14-bit digital words at rates up to 80 Mega Samples Per Second (MSPS). More...


Applications


High IF Sampling Receivers
Wireless Base Station Receivers
Test and Measurement Equipment
Communications Instrumentation
Portable Instrumentation
  Typical Application
click for larger image


ParametersValues
Resolution 14 bits
Channels 2 Channels
SNR 74.2 dB
SFDR 90 dB
ENOB 12 bits
Max Sample Rate 80 MSPS
Min Sample Rate 20 MSPS
Power Dissipation 0.845 Watt
PowerWise Rating 1 1.29 pJ/conv
INL (+/-) 1.5 LSB
SINAD 74 dB
DNL (+/-) 0.5 LSB
THD dB -88 dB
Min Supply Voltage 2.7 Volt
Max Supply Voltage 3.6 Volt
Nominal Vin 2 Vpp
Temperature Min -40 deg C
Temperature Max 85 deg C
Data Converter Type ADC
Automotive Yes
PowerWise Yes


Typical Performance


click for larger image

DNL
  Also Recommended
LMH6515DVGA
LMH6552Differential Amplifier, As Seen In ADC14DS105KARB Reference Design
LMK02000Low-jitter Clock Conditioner, As Seen In ADC14DS105KARB Reference Design
Additional Resources
Design Tools


Block Diagram


click for larger image

Block Diagram

Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
ADC14DS080 Dual 14-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs 598
Kbytes
14-Dec-07 Download
ADC14DS080 Dual 14-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs (Japanese)
496 Kbytes   Download

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Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
Format
TypePinsSpec.MSL
Rating
Peak
Reflow
RoHS
Report
CAD
Symbols
WeeksQtyQty$US each
ADC14DS080LFEBevaluation boardFull productionN/A
 
Buy Now
1+$495.001-
N/AN/A
ADC14DS080CISQLLP60NOPB3260RoHS Download Full productionN/A
Samples
Buy Now
1K+$36.00reel
of
2000
NS
UZXYTTE#
14DS080
6 weeksN/A

General Description


The ADC14DS080 is a high-performance CMOS analog-to-digital converter capable of converting two analog input signals into 14-bit digital words at rates up to 80 Mega Samples Per Second (MSPS). The digital outputs are serialized and provided on differential LVDS signal pairs. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC14DS080 may be operated from a single +3.0V or 3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14DS080 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. A serial interface allows access to the control registers for full control of the ADC14DS80 functionality. The ADC14DS080 is available in a 60-lead LLP package and operates over the industrial temperature range of −40°C to +85°C.

Design Tools


TitleSize in Kbytes Date Click link below to Download    
Evaluation Boards & Development Systems     View    

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[Information as of 7-Nov-2009]