Datasheet
RoHS Compliance Information
| Size in Kbytes | Date |
 |
| ADC14155 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter |
462
Kbytes |
28-Apr-09 |
Download |
ADC14155 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter (Japanese)
 |
671 Kbytes |
|
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Package Availability, Models, Samples & Pricing
| Part Number | Package | Factory Lead Time | Models | Samples &
Electronic
Orders | Budgetary Pricing | Std
Pack
Size | Package
Marking
Format |
| Type | Pins | Spec. | MSL
Rating | Peak
Reflow | RoHS
Report | CAD
Symbols | Weeks | Qty | Qty | $US each |
| ADC14155HFEB | ADC14155 evaluation board for input frequencies greater than 150 MHz | Full production | N/A
|
| 1+ | $495.00 | 1 | - |
| N/A | N/A |
| ADC14155LFEB | ADC14155 evaluation board for input frequencies less than 150 MHz | Full production | N/A
|
| 1+ | $495.00 | 1 | - |
| N/A | N/A |
| ADC14155CISQ | LLP | 48 | NOPB
STD | 3
3 | 260
260 | RoHS |
Download |
Full production | N/A
|
| 1K+ | $67.10 | reel
of
250 | NS
UZXYTTE#
14155SQ |
| 16 weeks | 500 |
| Obsolete Part | Alternate Part or
Supplier | Source | Last Time Buy Date |
ADC14155CISQE
| ADC14155CISQ
| NATIONAL SEMICONDUCTOR
| 29 May 2008
|
General Description
The ADC14155 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit
digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture
with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component
count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1
GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 967 mW of power at 155 MSPS.
The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature
reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation.
The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V
internal voltage reference is provided, or the ADC14155 can be operated with an external reference.
The ADC14155 can be configured for either single-ended or differential operation. Clock mode (differential versus single-ended)
and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance
over a wide range of clock duty cycles.
The ADC14155 is available in a 48-lead LLP package and operates over the industrial temperature range of −40°C to +85°C.
Reliability Metrics
| Part Number |
Process |
EFR Reject |
EFR Sample Size |
PPM |
LTA Rejects |
LTA Device Hours |
FITS |
MTTF (Hours) |
|
ADC14155CISQ | CMOS9 | 1 | 7327 | 137 | 0 | 1103000 | 4 | 312979261
|
Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR.
The Long Term Failure Rates were calculated
at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress
temperature of 150°C to an application temperature of 55°C.
For more information on Reliability Metrics, please click here.
Design Tools
| Title | Size in Kbytes |
Date |
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| Evaluation Boards & Development Systems |
|
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View |
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Application Notes
| Title | Size in Kbytes |
Date |
|
| AN-1721: Application Note 1721 High Speed ADCs with Interfacing, Driving and Clocking Schemes |
186
Kbytes |
20-Sep-07 |
Download |
AN-1721 (Japanese): Application Note 1721 High Speed ADCs with Interfacing, Driving and Clocking Schemes
 |
256 Kbytes |
|
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AN-1721 (Chinese): Application Note 1721 High Speed ADCs with Interfacing, Driving and Clocking Schemes
|
399 Kbytes |
|
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[Information as of 7-Nov-2009]
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