Features • 1.1 GHz Full Power Bandwidth • Internal sample-and-hold circuit • Internal precision 1.0V reference • Single-ended or Differential clock modes • Clock Duty Cycle Stabilizer • Dual +3.3V and +1.8V supply operation • Power-down and Sleep modes • Offset binary or 2's complement output data format • LVDS outputs • Pin-compatible: ADC14V155 • 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch) Description The ADC12V170 is a high-performance CMOS analog-to-digital converter with LVDS outputs. It is capable of converting analog input signals into 12-Bit digital words at rates up to 170 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data Rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC12V170 operates from dual +3.3V and +1.8V power supplies and consumes 781 mW of power at 170 MSPS. The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 15 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time. The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC12V170 can be operated with an external reference. Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles. The ADC12V170 is pin-compatible with the ADC14V155. It is available in a 48-lead LLP package and operates over the industrial temperature range of −40°C to +85°C. Key Specification Resolution 12 Bits Conversion Rate 170 MSPS SNR (fIN = 70 MHz) 67.2 dBFS (typ) SFDR (fIN = 70 MHz) 85.8 dBFS (typ) ENOB (fIN = 70 MHz) 10.9 bits (typ) Full Power Bandwidth 1.1 GHz (typ) Power Consumption 781 mW (typ) Applications • High IF Sampling Receivers • Wireless Base Station Receivers • Power Amplifier Linearization • Multi-carrier, Multi-mode Receivers • Test and Measurement Equipment • Communications Instrumentation • Radar Systems

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Typical Application *click for larger image application circuit	Block Diagram *click for larger image block diagram
Typical Performance *click for larger image noise vs. fin

Datasheet

Title		Size	Date	Other Language
	ADC12V170 12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs	607 Kbytes	27-Apr-09	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-929: Application Note 929 Microcontroller Interface to the ADC12038 Families	349 Kbytes	20-Sep-02

More Application Notes

Title		Size	Date	Other Language
	AN-1261: Application Note 1261 Power Supply Effects on Noise Performance	78 Kbytes	16-Mar-07	中文

Part Number(s) (NSID)	Top View	Availability	Current Reported Stock	Budgetary Pricing	Standard Pack Size
ADC12V170CISQ/NOPB ADC12V170CISQ RoHS		Full production Lead Time: 16 weeks	Distributor Region Qty DIGIKEY Worldwide 500 NEWARK Americas 205	$33.00 each at 1K+ pcs	reel of 250

Obsolete Versions

Obsolete Part	Alternate Part or Supplier	Source	Last Time Buy Date
ADC12V170CISQE	ADC12V170CISQ	NATIONAL SEMICONDUCTOR	29 May 2008

Design Tools

Title	Size	Date
Evaluation Boards & Development Systems

Obsolete Versions

Obsolete Part	Alternate Part or Supplier	Source	Last Time Buy Date
ADC12V170CISQE	ADC12V170CISQ	NATIONAL SEMICONDUCTOR	29 May 2008