Features • 1 GHz Full Power Bandwidth • Internal reference and sample-and-hold circuit • Low power consumption • Data Ready output clock • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V supply operation • Power-down mode • 32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch) Description The ADC12C105 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12C105 may be operated from a single +3.0V or +3.3V power supply and consumes low power. A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12C105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC12C105 is available in a 32-lead LLP package and operates over the industrial temperature range of −40°C to +85°C. Key Specification Resolution 12 Bits Conversion Rate 105 MSPS SNR (fIN = 240 MHz) 69 dBFS (typ) SFDR (fIN = 240 MHz) 82 dBFS (typ) Full Power Bandwidth 1 GHz (typ) Power Consumption 350 mW (typ), VA=3.0V 400 mW (typ), VA=3.3V Applications • High IF Sampling Receivers • Wireless Base Station Receivers • Test and Measurement Equipment • Communications Instrumentation • Portable Instrumentation

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Typical Application click for larger image Application Circuit	Block Diagram click for larger image
Typical Performance click for larger image DNL

Datasheet

Title		Size	Date	Other Language
	ADC12C105 12-Bit, 95/105 MSPS A/D Converter	455 Kbytes	22-Aug-07	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-769: Dynamic Specifications for Sampling A/D Converters	128 Kbytes	5-Aug-95

More Application Notes

Title		Size	Date	Other Language
	AN-1261: Application Note 1261 Power Supply Effects on Noise Performance	78 Kbytes	16-Mar-07	中文

Design Tools

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Evaluation Boards & Development Systems

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
ADC12C105CISQX	CMOS9	1	7327	137	0	1103000	4	312979261

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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