Offset binary or 2's complement output data format.
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LVDS or CMOS output signals.
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60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)
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Clock Duty Cycle Stabilizer.
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IF Sampling Bandwidth > 900MHz.
Description
The
ADC10DV200 is a monolithic analog-to-digital converter capable of converting two analog input signals into 10-bit digital words at rates
up to 200 Mega Samples Per Second (MSPS). The digital output mode is selectable and can be either differential LVDS or CMOS
signals. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold
circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold
stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the
ADC10DV200 may be operated from a single 1.8V power supply. The
ADC10DV200 achieves approximately 9.6 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode and 450mW at 200MSPS
in LVDS mode. The power consumption can be scaled down further by reducing sampling rates.
ADC10DV200
