Features • Internal sample-and-hold • Internal reference capability • Dual gain settings • Offset correction • Selectable offset binary or 2's complement output • Multiplexed or parallel output bus • Single +2.7V to 3.6V operation • Power down and standby modes Description The ADC10D020 is a dual low power, high performance CMOS analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rates up to 30 MSPS while consuming a typical 150 mW from a single 3.0V supply. No missing codes is guaranteed over the full operating temperature range. The unique two stage architecture achieves 9.5 Effective Bits over the entire Nyquist band at 20 MHz sample rate. An output formatting choice of offset binary or 2's complement coding and a choice of two gain settings eases the interface to many systems. Also allowing great flexibility of use is a selectable 10-bit multiplexed or 20-bit parallel output mode. An offset correction feature minimizes the offset error. To ease interfacing to most low voltage systems, the digital output power pins of the ADC10D020 can be tied to a separate supply voltage of 1.5V to 3.6V, making the outputs compatible with other low voltage systems. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 1 mW and from which recovery is less than 1 ms. Bringing the STBY (Standby) pin high places the converter into a standby mode where power consumption is about 27 mW and from which recovery is 800 ns. The ADC10D020's speed, resolution and single supply operation makes it well suited for a variety of applications, including high speed portable applications. Operating over the industrial (-40° <= TA <= +85°C) temperature range, the ADC10D020 is available in a 48-pin TQFP. An evaluation board is available to ease the design effort. Key Specification Resolution 10 Bits Conversion Rate 20 MSPS ENOB 9.5 Bits (typ) DNL 0.35 LSB (typ) Conversion Latency Parallel Outputs 2.5 Clock Cycles Multiplexed Outputs, I Data Bus 2.5 Clock Cycles Multiplexed Outputs, Q Data Bus 3 Clock Cycles PSRR 90 dB Power Consumption-Normal Operation 150 mW (typ) Power Down Mode <1 mW (typ) Fast Recovery Standby Mode 27 mW (typ)

Also Recommended ADC10D040▲ Faster (40Msps) MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

	Block Diagram click for larger image
Typical Performance click for larger image

Datasheet

Title		Size	Date	Other Language
	ADC10D020 Dual 10-Bit, 20 MSPS, 150 mW A/D Converter	1233 Kbytes	25-Feb-05	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-769: Dynamic Specifications for Sampling A/D Converters	128 Kbytes	5-Aug-95

More Application Notes

Title		Size	Date	Other Language
	AN-769: Dynamic Specifications for Sampling A/D Converters	128 Kbytes	5-Aug-95

Design Tools

Title	Size	Date
Evaluation Boards & Development Systems

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
ADC10D020CIVS	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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