Features • Single +3.0V operation • Selectable 2 VP-P, 1.5 VP-P, or 1 VP-P full-scale input • 400 MHz −3 dB input bandwidth • Low power consumption • Standby mode • On-chip reference and sample-and-hold amplifier • Offset binary or two’s complement data format • Separate adjustable output driver supply to accommodate 2.5V and 3.3V logic families • 28-pin TSSOP package Description The ADC10065 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 68.4 mW at 65 MSPS, including the reference current. The Standby feature reduces power consumption to just 14 .1 mW. The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement. This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C. Key Specification Resolution 10 Bits Conversion Rate 65 MSPS Full Power Bandwidth 400 MHz DNL ±0.3 LSB (typ) SNR (fIN = 11 MHz) 59.6 dB (typ) SFDR (fIN = 11 MHz) −80 dB (typ) Power Consumption, 65 MHz 68.4 mW Applications • Ultrasound and Imaging • Instrumentation • Cellular Base Stations/Communications Receivers • Sonar/Radar • xDSL • Wireless Local Loops • Data Acquisition Systems • DSP Front Ends

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	Block Diagram click for larger image
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Datasheet

Title		Size	Date	Other Language
	ADC10065 10-Bit 65 MSPS 3V A/D Converter	435 Kbytes	1-Feb-08	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-769: Dynamic Specifications for Sampling A/D Converters	128 Kbytes	5-Aug-95

More Application Notes

Title		Size	Date	Other Language
	AN-769: Dynamic Specifications for Sampling A/D Converters	128 Kbytes	5-Aug-95

Design Tools

Title	Size	Date
Evaluation Boards & Development Systems

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
ADC10065CIMT	CMOS9	1	7327	137	0	1103000	4	312979261
ADC10065CIMTX	CMOS9	1	7327	137	0	1103000	4	312979261

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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