ADC10040 - 10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter from the PowerWise® Family
Datasheet Packaging Samples & Pricing Reliability Design Tools Knowledge Base

Features
Single +3.0V operation
Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing
400 MHz −3 dB input bandwidth
Low power consumption
Standby mode
On-chip reference and sample-and-hold amplifier
Offset binary or two’s complement data format
Separate adjustable output driver supply to accommodate 2.5V and 3.3V logic families
AEC-Q100 Grade 3 Qualified
28-pin TSSOP package

Key Specification


Resolution

10 Bits

Conversion Rate

40 MSPS

Full Power Bandwidth

400 MHz

DNL

±0.3 LSB (typ)

SNR (fIN = 11 MHz)

59.6 dB (typ)

SFDR (fIN = 11 MHz)

−80 dB (typ)

Power Consumption, 40 MHz

55.5 mW

General Description


The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). More...


Applications


Ultrasound and Imaging
Instrumentation
Cellular Base Stations/Communications Receivers
Sonar/Radar
xDSL
Wireless Local Loops
Data Acquisition Systems
DSP Front Ends
  Typical Application
click for larger image

Differential Drive Circuit

ParametersValues
Resolution 10 bits
Channels 1 Channels
SNR 59.6 dB
SFDR 80 dB
ENOB 9.6 bits
Max Sample Rate 40 MSPS
Min Sample Rate 20 MSPS
Power Dissipation 0.0555 Watt
PowerWise Rating 1 1.79 pJ/conv
INL (+/-) 0.3 LSB
SINAD 59.5 dB
DNL (+/-) 0.3 LSB
THD dB -78 dB
Min Supply Voltage 2.7 Volt
Max Supply Voltage 3.6 Volt
Nominal Vin 1.5 Vpp
Temperature Min -40 deg C
Temperature Max 85 deg C
Data Converter Type ADC
AEC Q-100 Automotive Grade 3
Automotive Yes
PowerWise Yes


Typical Performance


click for larger image


  Also Recommended
ADC10065For Higher Speed
ADC10080For Higher Speed
ADC10D040For Dual ADC
Additional Resources
Design Tools


Block Diagram


click for larger image



Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
ADC10040/ADC10040Q 10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter 457
Kbytes
20-Oct-09 Download
ADC10040/ADC10040Q 10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter (Japanese)
715 Kbytes   Download

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Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
Format
TypePinsSpec.MSL
Rating
Peak
Reflow
RoHS
Report
CAD
Symbols
WeeksQtyQty$US each
ADC10040CIMTTSSOP28NOPB3260RoHS Download Full productionN/A
Samples
Buy Now
1K+$3.75rail
of
48
NSUZXYTTE#
ADC10040
CIMT
6 weeks500
ADC10040CIMTXTSSOP28NOPB3260RoHS Download Full productionN/A
 
Buy Now
1K+$3.75reel
of
2500
NSUZXYTTE#
ADC10040
CIMT
12 weeks3000

General Description


The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 55.5 mW at 40 MSPS, including the reference current. The Standby feature reduces power consumption to just 13.5 mW.

The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement.

The ADC10040Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 3 Qualified.

This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C.

Reliability Metrics


Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
ADC10040CIMTCMOS917327137011030004312979261
ADC10040CIMTXCMOS917327137011030004312979261

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


Design Tools


TitleSize in Kbytes Date Click link below to Download    
Evaluation Boards & Development Systems     View    

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[Information as of 8-Nov-2009]