Features • Internal Sample-and-Hold • Single +1.9V ±0.1V Operation • Choice of SDR or DDR output clocking • Interleave Mode for 2x Sampling Rate • Multiple ADC Synchronization Capability • Guaranteed No Missing Codes • Serial Interface for Extended Control • Fine Adjustment of Input Full-Scale Range and Offset • Duty Cycle Corrected Sample Clock Description The ADC08D500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 800 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10 -18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 1 GSPS ADC. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range. Key Specification Resolution 8 Bits Max Conversion Rate 500 MSPS (min) Bit Error Rate 10 -18 (typ) ENOB @ 250 MHz Input 7.5 Bits (typ) DNL ±0.15 LSB (typ) Power Consumption Operating 1.4 W (typ) Power Down Mode 3.5 mW (typ) Applications • Direct RF Down Conversion • Digital Oscilloscopes • Satellite Set-top boxes • Communications Systems • Test Instrumentation

Also Recommended ADC08200 For Single 200 Msps ADC08500▲ For Single Version ADC08B200 For Single 200 Mspswith Buffer ADC08D1000▲ For 1.0 Gsps Version ADC08D1500▲ For 1.5 Gsps Version LMH6518 Data Acquisition / Oscilloscope Front End LMH6555 For Analog Input Amplifier / Single-Ended To Differential Conversion MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

	Block Diagram *click for larger image
Typical Performance *click for larger image

Datasheet

Title		Size	Date	Other Language
	ADC08D500 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter	1031 Kbytes	20-Apr-09	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1558: Application Note 1558 Clocking High-Speed A/D Converters	659 Kbytes	17-Mar-07	日本語 中文

More Application Notes

Title		Size	Date	Other Language
	AN-281: AN-281 Data Acquisition Using INS8048	129 Kbytes	4-Oct-04

Design Tools

Title	Size	Date
Evaluation Boards & Development Systems
National GHz ADC Development Platform for Xilinx FPGAs

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
ADC08D500CIYB	CMOS9	1	7327	137	0	1103000	4	312979261

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

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