Datasheet
RoHS Compliance Information
| Size in Kbytes | Date |
 |
| ADC08D500 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter |
1031
Kbytes |
20-Apr-09 |
Download |
ADC08D500 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter (Japanese)
 |
1318 Kbytes |
|
 |
Package Availability, Models, Samples & Pricing
General Description
The ADC08D500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution
at sampling rates up to 800 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is
guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture,
the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration
scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input
signal and a 500 MHz sample rate while providing a 10
-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception
of an adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the
sampling rate. The two converters can be interleaved and used as a single 1 GSPS ADC.
The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced
exposed pad LQFP and operates over the Industrial (-40°C
≤ TA
≤ +85°C) temperature range.
Reliability Metrics
| Part Number |
Process |
EFR Reject |
EFR Sample Size |
PPM |
LTA Rejects |
LTA Device Hours |
FITS |
MTTF (Hours) |
|
ADC08D500CIYB | CMOS9 | 1 | 7327 | 137 | 0 | 1103000 | 4 | 312979261
|
Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR.
The Long Term Failure Rates were calculated
at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress
temperature of 150°C to an application temperature of 55°C.
For more information on Reliability Metrics, please click here.
Design Tools
| Title | Size in Kbytes |
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| Evaluation Boards & Development Systems |
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| National GHz ADC Development Platform for Xilinx FPGAs |
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[Information as of 7-Nov-2009]
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