ADC08500 - High Performance, Low Power 8-Bit, 500 MSPS A/D Converter from the PowerWise® Family
Datasheet Packaging Samples & Pricing Eval. Boards Reliability Knowledge Base

Features
Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Choice of SDR or DDR output clocking
Multiple ADC Synchronization Capability
Guaranteed No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock

Key Specification


Resolution

8 Bits

Max Conversion Rate

500 MSPS (min)

Bit Error Rate

10 -18 (typ)

ENOB @ 250 MHz Input

7.5 Bits (typ)

DNL

±0.15 LSB (typ)

Power Consumption

Operating

0.8 W (typ)

Power Down Mode

3.5 mW (typ)

General Description


The ADC08500 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. More...


Applications


Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
  Typical Application
*click for larger image

AC couple balun circuit

ParametersValues
Resolution 8 bits
Channels 1 Channels
SNR 47.5 dB
SFDR 56 dB
ENOB 7.5 bits
Max Sample Rate 500 MSPS
Min Sample Rate 200 MSPS
Power Dissipation 0.8 Watt
PowerWise Rating 1 8.84 pJ/conv
DNL (+/-) 0.15 LSB
INL (+/-) 0.3 LSB
SINAD 47 dB
THD dB -56 dB
Min Supply Voltage 1.8 Volt
Max Supply Voltage 2 Volt
Nominal Vin 0.7 Vpp
Temperature Min -40 deg C
Temperature Max 85 deg C
Data Converter Type ADC
Automotive No
PowerWise Yes


Typical Performance


*click for larger image


  Also Recommended
ADC081000For 1.0 Gsps
ADC081500For 1.5 Gsps
ADC08200For 200 Msps ADC
ADC08B200For 200 Msps ADC With Buffer
ADC08D500For Dual Version
LMH6555For Analog Input Amplifier / Single-Ended To Differential Conversion
Block Diagram
click for larger image



Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
ADC08500 High Performance, Low Power 8-Bit, 500 MSPS A/D Converter 975
Kbytes
21-Apr-09 Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.


Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
Format
TypePinsSpec.MSL
Rating
Peak
Reflow
RoHS
Report
CAD
Symbols
WeeksQtyQty$US each
ADC08500DEVADC08500DEV Evaluation BoardFull productionN/A
 
Buy Now
1+$4900.001-
8 weeksN/A
ADC08500CIYBLQFP EXP PAD128NOPB
STD
3
3
260
260
RoHS N/A Full productionN/A
 
Buy Now
25+$36.00tray
of
60
NSUZXYYTTE#
ADC08500CIYB
6 weeks500

General Description


The ADC08500 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 0.8 Watts at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10 -18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

The converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C TA +85°C) temperature range.

Reliability Metrics


Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
ADC08500CIYBCMOS917327137011030004312979261

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


[Information as of 7-Nov-2009]