Features • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test mode. • Clock recovery from PLL lock to random data patterns. • Guaranteed transition every data transfer cycle • Chipset (Tx + Rx) power consumption < 600 mW (typ) @ 80 MHz • Single differential pair eliminates multi-channel skew • 800 Mbps serial Bus LVDS data rate (at 80 MHz clock) • 10-bit parallel interface for 1 byte data plus 2 control bits • Synchronization mode and LOCK indicator • Programmable edge trigger on clock • High impedance on receiver inputs when power is off • Bus LVDS serial output rated for 27 load • Small 49-lead BGA package Description The SCAN921025 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The SCAN921226 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock. Both devices are compliant with IEEE 1149.1 Standard for Boundary Scan Test. IEEE 1149.1 features provide the design or test engineer access via a standard Test Access Port (TAP) to the backplane or cable interconnects and the ability to verify differential signal integrity. The pair of devices also features an at-speed BIST mode which allows the interconnects between the Serializer and Deserializer to be verified at-speed. The SCAN921025 transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the SCAN921025 output pins into TRI-STATE to achieve a high impedance state. The PLL can lock to frequencies between 30 MHz and 80 MHz.

Also Recommended SCAN921025H▲ High Temperature 20MHz - 80MHz 10-Bit Serializer With IEEE 1149.1 Test Access MY BRIEFCASE                                       Click any "Briefcase" icon to add an item

	Block Diagram click for larger image

Datasheet

Title		Size	Date	Other Language
	SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST	907 Kbytes	19-Nov-04	日本語

Featured Application Notes

Title		Size	Date	Other Language
	AN-1313: Application Note 1313 SCAN90CP02 Design for Test Features	428 Kbytes	11-Mar-05	中文

More Application Notes

Title		Size	Date	Other Language
	AN-770: PC16552C Dual UART/DMA Micro Channel Adapter	355 Kbytes	5-Aug-95

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
SCAN921025SLC	CMOS8	1	13140	55	0	1615500	3	458102536

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.