| • | Direct interface to the NS32FX161, NS32FV16 and NS32FX164 embedded processors |
| • | Supports a variety of Contact Image Sensor (CIS) and Charge Coupled Device (CCD) scanners |
| • | Direct interface to a variety of Thermal Print Head (TPH) printers. Bitmap shifter and DMA channels facilitate the connection of other types of printers |
| • | Supports two stepper motors |
| • | Direct interface to ROM and SRAM. The NS32FX200 and NS32FV100, in addition, interface to DRAM devices |
| • | Programmable wait state generator |
| • | Demultiplexed address and data buses |
| • | Multiplexed DRAM address bus (NS32FX200 and NS32FV100) |
| • | Supports 3V freeze mode by maintaining only elapsed time counter |
| • | Control of power consumption by disabling inactive modules and reducing the clock frequency |
| • | Operating frequency
|
| • | Normal mode: 19.6608 MHz-24.576 MHz in steps of 1.2288 MHz. (NS32FX200) |
| • | Normal mode: 19.6608 MHz-24.576 MHz in steps of 1.2288 MHz. (NS32FV100) |
| • | Normal mode: 14.7456 MHz-19.6608 MHz in steps of 1.2288 MHz. (NS32FX100) |
| • | Power Save mode: Normal mode frequency divided by sixteen |
| • | On-Chip full duplex Sigma-Delta CODEC with:
|
| • | Total harmonic distortion better than -70 dB |
| • | Programmable hybrid balance filter |
| • | Programmable reception and transmission filters |
| • | Programmable gain control |
| • | On-Chip Interrupt Control Unit with:
|
| • | 16 interrupt sources |
| • | Programmable triggering mode |
| • | On-Chip counters, WATCHDOG™, UART, MICROWIRE™, System Clock Generator, and I/O ports |
| • | On-Chip DMA controller (NS32FX200-four channels, NS32FX100, NS32FV100-three channels) |
| • | Up to 37 on-chip general purpose I/O pins, expandable externally |
| • | Flexible allocation of I/O and modules' pins |
| • | 132-pin JEDEC PQFP package |
RoHS Compliance Information