LMX3161 - Single Chip Radio Transceiver [Obsolete]
Datasheet Obsolete Versions Design Tools Application Notes Knowledge Base

Features
Single chip solution for DECT RF transceiver
RF sensitivity to -93 dBm; RSSI sensitivity to -100 dBm
Two regulated voltage outputs for discrete amplifiers
High gain (85 dB) intermediate frequency strip
Allows unregulated 3.0V-5.5V supply voltage
Power down mode for increased current savings
System noise figure 6.5 dB (typ)

 

General Description


The LMX3161 Single Chip Radio Transceiver is a monolithic, integrated radio transceiver optimized for use in a Digital Enhanced Cordless Telecommunications (DECT) system. More...


Applications


Digital Enhanced Cordless Telecommunications (DECT)
Personal wireless communications (PCS/PCN)
Wireless local area networks (WLANs)
Other wireless communications systems

Additional Resources


Design Tools

Application Notes



Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
LMX3161 Single Chip Radio Transceiver 212
Kbytes
22-Nov-99 Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Obsolete Versions

Obsolete PartAlternate Part or SupplierSourceLast Time Buy Date
LMX3161VBH
NONE
NONE
03 Jun 2003
LMX3161VBHX
NONE
NONE
03 Jun 2003

General Description


The LMX3161 Single Chip Radio Transceiver is a monolithic, integrated radio transceiver optimized for use in a Digital Enhanced Cordless Telecommunications (DECT) system. It is fabricated using National's ABiC V BiCMOS process (fT = 18 GHz).

The LMX3161 contains phase locked loop (PLL), transmit and receive functions. The 1.1 GHz PLL block is shared between transmit and receive section. The transmitter includes a frequency doubler, and a high frequency buffer. The receiver consists of a 2.0 GHz low noise mixer, an intermediate frequency (IF) amplifier, a high gain limiting amplifier, a frequency discriminator, a received signal strength indicator (RSSI), and an analog DC compensation loop. The PLL, doubler, and buffers can be used to implement open loop modulation along with an external VCO and loop filter. The circuit features on-chip voltage regulation to allow supply voltages ranging from 3.0V to 5.5V. Two additional voltage regulators provide a stable supply source to external discrete stages in the Tx and Rx chains.

The IF amplifier, high gain limiting amplifier, and discriminator are optimized for 110 MHz operation, with a total IF gain of 85 dB. The single conversion receiver architecture provides a low cost, high performance solution for communications systems. The RSSI output may be used for channel quality monitoring.

The Single Chip Radio Transceiver is available in a 48-pin 7mm X 7mm X 1.4mm PQFP surface mount plastic package.

Design Tools


TitleSize in Kbytes Date Click link below to Download    
PLL Codeloader Driver Software     View    

If you have trouble printing or viewing PDF file(s), see Printing Problems.

More Application Notes


TitleSize in Kbytes Date Click link below to Download
AN-1162: AN-1162 Using the LMX3162 for 2.4-GHz ISM Band 370
Kbytes
1-May-04 Download
AN-1166: Application Note 1166 Using the LMX5001 Bluetooth Link Controller 215
Kbytes
1-May-04 Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 8-Nov-2009]