Features
| • | CPU Display Interface support up to 800
x 300 ½SVGA formats |
| • | Dual displays supported - CS1* &
CS2* |
| • | MPL-Level 0 Physical Layer using two data
and one clock signal |
| • | Low Power Consumption |
| • | Pinout mirroring enables straight through
layout with minimal vias |
| • | Level translation between host and display |
| • | Link power down mode reduces quiescent power under <
10 µA |
| • | 1.74V to 2.0V core / analog supply voltage
range |
| • | 1.74V to 3.0V I/O supply voltage range |
Description The LM2507 device adapts i80 CPU style display interfaces to
the Mobile Pixel Link (MPL) Level zero serial link. When using smart CPU type
interfaces, two chip selects support a main and sub display. A mode pin configures
the device as a Master (MST) or Slave (SLV) so the same chip can be used on
both sides of the interface.
The interconnect is reduced from 21 signals to only 3 active
signals with the LM2507 chipset easing flex interconnect design, size constraints
and cost.
The LM2507 in MST mode resides beside an application, graphics
or baseband processor and translates a parallel bus from LVCMOS levels to
serial Mobile Pixel Link levels for transmission over a flex cable (or coax)
and PCB traces to the SLV located near the display module(s).
When the Power_Down (PD*) input is asserted on the Master,
the MDn and MC line drivers are powered down to save current. The Slave is
controlled by a separate Power_Down input.
The LM2507 implements the physical layer of the MPL Level
0 Standard (MPL-0) and a 150 µA IB current (Class 0).
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