| | Input frequency range from 30 MHz to 85 MHz |
| | Support display resolutions SXGA (1280x1024), SXGA+ (1400x1050) and UXGA (1600x1200) |
| | Embedded gate array for custom panel timing |
| | RSDS (Reduced Swing Differential Signaling) Column Driver bus for low power and reduced EMI |
| | Drives RSDS column driver up to 170 Mb/s with an 85 MHz clock |
| | 6 or 8 bit LVDS dual pixel input interface (FPD-Link) |
| | Virtual 8-bit color depth in FRC mode |
| | Flexible RSDS data output mapping for Bottom or Top mount |
| | Supports 1 and 2 line inversion mode for RVS output |
| | Supports Graphics Controllers with spread spectrum interface for lower EMI |
| | Free Run Mode Function |
| | Fail-safe function in DE mode (Bonding Option) |
| | Supports DE mode and SYNC only mode (Bonding Option) |
| | Power-On-Reset Support |
| | CMOS circuitry operates from a 2.7V to 3.6V supply |
| | Operation frequency: 54 MHz (max) @ VCC: 2.7 [Similar_To] 3.0V |
| | Operation frequency: 85 MHz (max) @ VCC: 3.0 [Similar_To] 3.6V |
| | 128 TQFP package with body size 14mm x 14mm x 1.0mm, 0.4mm Pitch |
The FPD87392AXA Panel Timing Controller is an integrated FPD-Link + RSDS + TFT-LCD Timing Controller. The logic architecture is implemented using standard and default timing controller functionality based on an Embedded Gate Array. The device is reconfigurable to the needs of a specific application by providing user-defined specifications or customer supplied VHDL/Verilog code.
The FPD87392AXA is a timing controller that combines an LVDS dual pixel input interface with National's Reduced Swing Differential Signaling (RSDS) output column driver interface for SXGA, SXGA+ and UXGA resolutions. It resides on the TFT-LCD panel and provides the data buffering and control signal generation. The RSDS data path to the column driver contributes toward lowering radiated EMI and reduced system dynamic power consumption. The RSDS dual 12 pair differential bus conveys up to 24-bit color data for SXGA/SXGA+/UXGA panels when using VESA 60Hz standard timing.