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Features
832 Mbps LVDS 16-bit serializer and deserializer interface
Suitable for cable, printed circuit board, and backplane transmission paths
10m cable at max LVDS data rate and greater than 16m at min LVDS data rate
Embedded clock with random data lock capability for clock recovery
PRBS (x
31 + x
28 + 1) based LVDS link BER test facility
Two independent LVDS receiver serial ports for optional 1:1 protection
Main and redundant LVDS transmit ports
Loop timing capability enables LVDS recovered clock to internally drive LVDS transmit clock
Internal buffers allow maximum LVDS serial bit rate independent of UTOPIA clock rate
Programmable UTOPIA interface
UTOPIA Level 2 up to 52 MHz
ATM layer or PHY layer interface
ATM layer interface can support up to 248 standard Level 2 PHY ports with no additional external circuitry. Configured as
31 MPHY’s, each with up to 8 sub-ports
Supports extended cell size up to 64 bytes
Supports 16- or 8-bit data buses with parity
Embedded bidirectional, non-blocking flow control over serial link for per MPHY back pressure
No external memories required
Embedded OAM channel over serial link
Remote Alarm/Status Indications
Link Trace Label
Embedded Control Channel with flow control for software communication
BIP16 based error performance monitoring
In protected systems, the standby link OAM channel is available for embedded communications and performance/alarm monitoring
Multiple loop-back options
Standard microprocessor interface (Intel and Motorola compatible)
IEEE 1149.1 JTAG port
Temperature range: −40°C to +85°C
CMOS technology for low power
LVDS transceiver section uses 3.3V power supply. Digital UTOPIA section uses 2.5V power supply. All I/O are 3.3V tolerant.
196 LBGA package, 15x15x1.37 mm, 1.0 mm ball pitch
Description The DS92UT16 is a flexible UTOPIA to LVDS Bridge device. The LVDS Bridge transparently transports the UTOPIA bus over a high
speed LVDS serial link. The device includes many reliability features such as an optional 1:1 protection and built in bit
error rate checking.
The parallel interface is user programmable for maximum flexibility. The user can choose between UTOPIA Level Level 2 ATM
layer (master) of PHY layer (slave). The UTOPIA-LVDS Bridge supports a special MPHY (multi-PHY layer) operation mode. The
MPHY operation supports up to 248 standard UTOPIA Level 2 PHY ports without adding external circuitry.
The serial interface uses LVDS Serializer and Deserializer technology. The 16:1 bit serialization allows conveying the full-duplex
parallel bus over two differential transmission pairs. This enables low cost backplanes and cables. Cable transmission length
can be as long 16 meters.
The serial link carries Flow control information (back pressure) in both directions. The Bridge device applies back pressure
on a per queue basis over the 31 internal FIFO queues. In addition, the serial link includes an OAM (Operations and Maintenance)
channel that does not detract from link performance.
There are many applications where the UTOPIA-LVDS Bridge simplifies designs. Box-to-box connections can use DS29UT16 devices
across cables. Access multiplexor applications can use the devices across a PCB backplane for point-to-point and lightly loaded
multidrop configurations.
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