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Features
66 MHz clock support
Up to 231 Mbytes/s bandwidth
Low power CMOS design (< 610 mW)
Power Down mode (< 0.5 mW total)
Up to 1.848 Gbit/s data throughput
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
PLL requires no external components
Low profile 56-lead TSSOP package
Rising edge data strobe
Compatible with TIA/EIA-644 LVDS Standard
Description The DS90CR283 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR284 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 Mbytes/s).
The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data bus and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.
The 28 CMOS/TTL inputs can support a variety of signal combinations. For example, 7 4-bit nibbles or 3 9-bit (byte + parity) and 1 control.
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