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Features
Up to 105 Megabyte/sec bandwidth
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
Low power CMOS design
Power down mode
PLL requires no external components
Low profile 48-lead TSSOP package
Falling edge data strobe
Compatible with TIA/EIA-644 LVDS standard
Description The DS90CF561 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.
A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and transmitted. The DS90CF562 receiver converts the LVDS data streams back
into 21 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 18 bits of RGB data and 3 bits of LCD timing and control
data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput
is 105 Megabytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety
of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
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