DS90CF562 - LVDS 18-Bit Color Flat Panel Display (FPD) Link [Life-time buy]
Datasheet Packaging Samples & Pricing Reliability Knowledge Base

Features
•Up to 105 Megabyte/sec bandwidth
•Narrow bus reduces cable size and cost
•290 mV swing LVDS devices for low EMI
•Low power CMOS design
•Power down mode
•PLL requires no external components
•Low profile 48-lead TSSOP package
•Falling edge data strobe
•Compatible with TIA/EIA-644 LVDS standard

 

General Description

The DS90CF561 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. More...


Also Recommended

DS90CF364A▲3V Supply

Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
DS90CF561/DS90CF562 LVDS 18-Bit Color Flat Panel Display (FPD) Link 242
Kbytes		 16-Aug-00 Download
DS90CF561/DS90CF562 LVDS 18-Bit Color Flat Panel Display (FPD) Link (Japanese)
 162 Kbytes   Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.


Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders		Budgetary PricingStd
Pack
Size		Package
Marking
Format
TypePinsSpec.MSL
Rating		Peak
Reflow		RoHS
Report		CAD
Symbols		WeeksQtyQty$US each
DS90CF562MTDTSSOP48NOPB
STD		2
2		260
235		RoHS N/A Lifetime buyN/A
 
Buy Now 		1K+$5.00rail
of
38		NSUZXYTT
DS90CF562MTD
BBBBB
6 weeks500
DS90CF562MTDXTSSOP48NOPB
STD		2
2		260
235		RoHS N/A Lifetime buyN/A
 
Buy Now 		1K+$5.00reel
of
1000		NSUZXYTT
DS90CF562MTD
BBBBB
6 weeks2000

Obsolete Versions

Obsolete PartAlternate Part or SupplierSourceLast Time Buy Date
DS90CF562MTD
DS90CF564
National Semiconductor
30 Nov 2009
DS90CF562MTDX
DS90CF564
National Semiconductor
30 Nov 2009

General Description

The DS90CF561 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF562 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 105 Megabytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety of graphics and LCD panel controllers.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

Reliability Metrics

Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
DS90CF562MTDCS0800305350028105002797458048
DS90CF562MTDXCS0800305350028105002797458048

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


[Information as of 8-Nov-2009]