DP8422A - microCMOS Programmable 4M Dynamic RAM Controller/Driver(s) [Obsolete]
Datasheet Obsolete Versions Knowledge Base

Features
On chip high precision delay line to guarantee critical DRAM access timing parameters
microCMOS process for low power
High capacitance drivers for RAS#, CAS#, WE# and DRAM address on chip
On chip support for nibble, page and static column DRAMs
Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic
Selection of controller speeds: 20 MHz and 25 MHz
On board Port A/Port B (DP8422A only)/refresh arbitration logic
Direct interface to all major microprocessors (application notes available)
4 RAS# and 4 CAS# drivers (the RAS# and CAS# configuration is programmable)

 

General Description


The DP8420A/21A/22A dynamic RAM controllers provide a low cost, single chip interface between dynamic RAM and all 8-, 16- and 32-bit systems. More...



Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
DP8420A/21A/22A microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers 824
Kbytes
20-Feb-97 Download

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Obsolete Versions

Obsolete PartAlternate Part or SupplierSourceLast Time Buy Date
DP8422ATV-25
NONE
NONE
06 Dec 2000
DP8422ATVX-25
NONE
NONE
02 Dec 2003
DP8422AV-20
NONE
NONE
06 Sep 2000
DP8422AV-25
NONE
NA
08 Mar 2005
DP8422AVX-20
NONE
NONE
06 Sep 2000
DP8422AVX-25
NONE
NA
08 Mar 2005

General Description


The DP8420A/21A/22A dynamic RAM controllers provide a low cost, single chip interface between dynamic RAM and all 8-, 16- and 32-bit systems. The DP8420A/21A/22A generate all the required access control signal timing for DRAMs. An on-chip refresh request clock is used to automatically refresh the DRAM array. Refreshes and accesses are arbitrated on chip. If necessary, a WAIT# or DTACK# output inserts wait states into system access cycles, including burst mode accesses. RAS# low time during refreshes and RAS# precharge time after refreshes and back to back accesses are guaranteed through the insertion of wait states. Separate on-chip precharge counters for each RAS# output can be used for memory interleaving to avoid delayed back to back accesses because of precharge. An additional feature of the DP8422A is two access ports to simplify dual accessing. Arbitration among these ports and refresh is done on chip.

[Information as of 8-Nov-2009]