DP83934 - SONIC-T Systems-Oriented Network Interface Controller with Twisted Pair Interface [Obsolete]
Datasheet Obsolete Versions Application Notes Knowledge Base

Features
32-bit non-multiplexed address and data bus
Auto AUI/TPI selection
High-speed interruptible DMA
Linked-list buffer management maximizes flexibility
Two independent 32-byte transmit and receive FIFOs
Bus compatibility for all standard microprocessors
Supports big and little endian formats
Integrated IEEE 802.3 ENDEC
Integrated Twisted Pair Interface
Complete address filtering for up to 16 physical and/or multicast addresses
32-bit general-purpose timer
Loopback diagnostics
Fabricated in low-power CMOS
160 PQFP package
Full network management facilities support the 802.3 layer management standard
Integrated support for bridge and repeater applications

 

General Description


The SONIC-T (Systems-Oriented Network Interface Controller with Twisted Pair) is a second-generation Ethernet Controller designed to meet the demands of today's high-speed 32- and 16-bit systems. More...


Additional Resources


Application Notes



Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
DP83934CVUL-20/25 MHz SONIC(TM)-T Systems-Oriented Network Interface Controller with Twisted Pair Interface 1104
Kbytes
7-Jan-96 Download

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Obsolete Versions

Obsolete PartAlternate Part or SupplierSourceLast Time Buy Date
DP83934AVQB
NONE
NATIONAL SEMICONDUCTOR
25 Oct 2005
DP83934CVUL-20
NONE
NATIONAL SEMICONDUCTOR
25 Oct 2005
DP83934CVUL-25
NONE
NATIONAL SEMICONDUCTOR
25 Oct 2005
DP83934CVUL-33
NONE
NATIONAL SEMICONDUCTOR
25 Oct 2005
DP83934CVUL-3V
NONE
NONE
25 Oct 2005

General Description


The SONIC-T (Systems-Oriented Network Interface Controller with Twisted Pair) is a second-generation Ethernet Controller designed to meet the demands of today's high-speed 32- and 16-bit systems. Its system interface operates with a high speed DMA that typically consumes less than 5% of the bus bandwidth. Selectable bus modes provide both big and little endian byte ordering and a clean interface to standard microprocessors. The linked-list buffer management system of SONIC-T offers maximum flexibility in a variety of environments from PC-oriented adapters to high-speed motherboard designs. Furthermore, the SONIC-T integrates a fully-compatible IEEE 802.3 Encoder/Decoder (ENDEC) and a Twisted Pair Interface which provide a one-chip solution for Ethernet when using 10BASE-T. When using 10BASE2 or 10BASE5, the SONIC-T may be paired with the DP8392 Coaxial Transceiver Interface to achieve a simple 2-chip solution.

For increased performance, the SONIC-T implements a unique buffer management scheme to efficiently process receive and transmit packets in system memory. No intermediate packet copy is necessary. The receive buffer management uses three areas in memory for (1) allocating additional resources, (2) indicating status information, and (3) buffering packet data. During reception, the SONIC-T stores packets in the buffer area, then indicates receive status and control information in the descriptor area. The system allocates more memory resources to the SONIC-T by adding descriptors to the memory resource area. The transmit buffer management uses two areas in memory:

1. indicating status and control information;

2. fetching packet data.

The system can create a transmit queue allowing multiple packets to be transmitted from a single transmit command. The packet data can reside on any arbitrary byte boundary and can exist in several non-contiguous locations.

More Application Notes


TitleSize in Kbytes Date Click link below to Download
AN-873: Architectural Choices for Network Performance 246
Kbytes
5-Aug-95 Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 8-Nov-2009]