DP83815 - 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter) <font color=red>[Not recommended for new designs]</font>

DP83815 - 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter) [Not recommended for new designs]

Datasheet	Packaging	Samples & Pricing	Reliability	Models	Knowledge Base

Features

•	IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy)
•	Bus master - burst sizes of up to 128 dwords (512 bytes)
•	BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
•	Wake on LAN (WOL) support compliant with PC98, PC99, SecureOn, and OnNow, including directed packets, Magic Packetš, VLAN packets, ARP packets, pattern match packets, and Phy status change
•	Clkrun function for PCI Mobile Design Guide
•	Virtual LAN (VLAN) and long frame support
•	Support for IEEE 802.3x Full duplex flow control
•	Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns
•	Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management
•	Internal 2 KB Transmit and 2 KB Receive data FIFOs
•	Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
•	Flash/PROM interface for remote boot support
•	Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer
•	IEEE 802.3 10BASE-T transceiver with integrated filters
•	IEEE 802.3u 100BASE-TX transceiver
•	Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
•	IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM
•	Full Duplex support for 10 and 100 Mb/s data rates
•	Single 25 MHz reference clock
•	144-pin LQFP and 160-pin LBGA packages
•	Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode
•	IEEE 802.3u MII for connecting alternative external Physical Layer Devices

General Description

DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. More...

Also Recommended

DP83816

For Latest Device

Datasheet

RoHS Compliance Information	Size in Kbytes	Date
DP83815 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter)	889 Kbytes	3-Oct-05	Download

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Package Availability, Models, Samples & Pricing

Part Number

Package

Factory Lead Time

Models

Samples &
Electronic
Orders

Budgetary Pricing

Std
Pack
Size

Package
Marking
Format

Type

Pins

Spec.

MSL
Rating

Peak
Reflow

RoHS
Report

CAD
Symbols

Weeks

Qty

$US each

DP83815DUJB

LBGA

160

NOPB
STD

3
3

260
220

RoHS

N/A

Not recommended for new designs
(as of 9-Jul-04)

dp83815u.ibs

1K+

$11.30

tray
of
119

NSUZXYYTTE#
DP83815DUJB

14 weeks

500

DP83815DVNG

LQFP

144

NOPB
STD

3
3

260
260

RoHS

N/A

Not recommended for new designs
(as of 4-Oct-02)

dp83815v.ibs

1K+

$7.44

tray
of
60

NSUZXYYTTE#
DP83815DVNG

6 weeks

100

Obsolete Versions

Obsolete Part	Alternate Part or Supplier	Source	Last Time Buy Date
DP83815-MAAP	NONE	NONE	02 Dec 2003
DP83815AVNG	NONE	NONE	04 Dec 2001
DP83815CVNG	NONE	NONE	22 Oct 2003
DP83815CVNG-PXE	NONE	NONE	02 Dec 2003
DP83815DUJB-AB	NONE	NATIONAL SEMICONDUCTOR	25 Oct 2005
DP83815DUJB-AP	NONE	NATIONAL SEMICONDUCTOR	25 Oct 2005
DP83815DVNG-AB	NONE	NATIONAL SEMICONDUCTOR	25 Oct 2005
DP83815DVNG-AP	NONE	NATIONAL SEMICONDUCTOR	25 Oct 2005
DP83815DVNG-PXE	NONE	NATIONAL SEMICONDUCTOR	05 Mar 2008

General Description

DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.

The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.

Reliability Metrics

Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DP83815DUJB	CMOS7	0	18406	0	0	1089000	4	309006723
DP83815DVNG	CMOS7	0	18406	0	0	1089000	4	309006723

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Application Notes

Title	Size in Kbytes	Date
AN-1323: AN-1323 Updating DP83815 MacPHYTER Hardware Designs to DP83816 MacPHYTER-II	108 Kbytes	17-Mar-04	Download
AN-1323 (Chinese): AN-1323 Updating DP83815 MacPHYTER Hardware Designs to DP83816 MacPHYTER-II	260 Kbytes
AN-1351: AN-1351 MAC Address Programming for DP83816 MacPHYTER-II and DP83815 MacPHYTER	134 Kbytes	5-Jan-05	Download
AN-1351 (Chinese): AN-1351 MAC Address Programming for DP83816 MacPHYTER-II and DP83815 MacPHYTER	255 Kbytes
AN-1287: AN-1287 DP83815 MacPHYTER and DP83816 MacPHYTER-II High Data Rate Stress Testing	46 Kbytes	18-Jun-03	Download
AN-1287 (Chinese): AN-1287 DP83815 MacPHYTER and DP83816 MacPHYTER-II High Data Rate Stress Testing	237 Kbytes

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[Information as of 8-Nov-2009]