Datasheet
RoHS Compliance Information
| Size in Kbytes | Date |
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| CLC018 8 x 8 Digital Crosspoint Switch, 1.485 Gbps |
667 Kbytes |
4-Aug-06 |
Download |
CLC018 8 x 8 Digital Crosspoint Switch, 1.485 Gbps (Japanese)
 |
460 Kbytes |
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Package Availability, Models, Samples & Pricing
| Obsolete Part | Alternate Part or
Supplier | Source | Last Time Buy Date |
CLC018AJVJQ
| LMH0024
| National Semiconductor
| 30 Nov 2009
|
CLC018PCASM
| NONE
| NONE
| 03 Sep 2002
|
General Description
The CLC018 is a fully differential 8x8 digital crosspoint switch capable of operating at data rates exceeding 1.485 Gbps per channel. Its non-blocking architecture utilizes eight independent 8:1 multiplexers to allow each output to be independently connected to any input and any input to be connected to any or all outputs. Additionally, each output can be individually disabled and set to a high-impedance state. This TRI-STATE feature allows flexible expansion to larger switch array sizes.
Low channel-to-channel crosstalk allows the CLC018 to provide superior all-hostile jitter of 50 psPP. This excellent signal fidelity along with low power consumption of 850 mW make the CLC018 ideal for digital video switching plus a variety of data communication and telecommunication applications.
The fully differential signal path provides excellent noise immunity, and the I/Os support ECL and PECL logic levels. In addition, the inputs may be driven single-ended or differentially and accept a wide range of common mode levels including the positive supply. Single +5V or -5V supplies or dual +5V supplies are supported. Dual supply mode allows the control signals to be referenced to the positive supply (+5V) while the high-speed I/O remains ECL compatible.
The double row latch architecture utilized in the CLC018 allows switch reprogramming to occur in the background during operation. Activation of the new configuration occurs with a single "configure" pulse. Data integrity and jitter performance on unchanged outputs are maintained during reconfiguration. Two reset modes are provided. Broadcast reset results in all outputs being connected to input port DI0. TRI-STATE Reset results in all outputs being disabled.
The CLC018 is fabricated on a high-performance BiCMOS process and is available in a 64-lead plastic quad flat pack (PQFP).
More Application Notes
| Title | Size in Kbytes |
Date |
 |
| AN-2004: Application Note 2004 Replacing the CLC016 Reclocker with the LMH0026 |
154 Kbytes |
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| AN-2002: Application Note 2002 Replacing the CLC014 Adaptive Cable Equalizer with the LMH0074 |
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| AN-1113: Application Note 1113 Serial Digital Video and Interface RAPIDESIGNER Operation and Applications Guide |
98 Kbytes |
4-Oct-04 |
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| AN-1347: Application Note 1347 PCB Layout Techniques for Adaptive Cable Equalizers |
498 Kbytes |
18-Nov-04 |
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AN-1347 (Chinese): Application Note 1347 PCB Layout Techniques for Adaptive Cable Equalizers
|
332 Kbytes |
|
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[Information as of 8-Nov-2009]
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