National Semiconductor | High-performance Analog

 

 CLC018   

8 x 8 Digital Crosspoint Switch, 1.485 Gbps [Obsolete]
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Features
  • Supports SMPTE 259M, SMPTE 344M, and SMPTE 292M
  • Fully differential signal path
  • Non-Blocking
  • Flexible expansion to larger array sizes with very low power
  • Single +5/-5V or dual ±5V operation
  • TRI-STATE outputs
  • Double row latch architecture
  • 64-lead PQFP package
  • Description

    The CLC018 is a fully differential 8x8 digital crosspoint switch capable of operating at data rates exceeding 1.485 Gbps per channel. Its non-blocking architecture utilizes eight independent 8:1 multiplexers to allow each output to be independently connected to any input and any input to be connected to any or all outputs. Additionally, each output can be individually disabled and set to a high-impedance state. This TRI-STATE feature allows flexible expansion to larger switch array sizes.

    Low channel-to-channel crosstalk allows the CLC018 to provide superior all-hostile jitter of 50 psPP. This excellent signal fidelity along with low power consumption of 850 mW make the CLC018 ideal for digital video switching plus a variety of data communication and telecommunication applications.

    The fully differential signal path provides excellent noise immunity, and the I/Os support ECL and PECL logic levels. In addition, the inputs may be driven single-ended or differentially and accept a wide range of common mode levels including the positive supply. Single +5V or -5V supplies or dual +5V supplies are supported. Dual supply mode allows the control signals to be referenced to the positive supply (+5V) while the high-speed I/O remains ECL compatible.

    The double row latch architecture utilized in the CLC018 allows switch reprogramming to occur in the background during operation. Activation of the new configuration occurs with a single "configure" pulse. Data integrity and jitter performance on unchanged outputs are maintained during reconfiguration. Two reset modes are provided. Broadcast reset results in all outputs being connected to input port DI0. TRI-STATE Reset results in all outputs being disabled.

    The CLC018 is fabricated on a high-performance BiCMOS process and is available in a 64-lead plastic quad flat pack (PQFP).

    Key Specification

  • High speed: >1.485 Gbps
  • Low jitter: <50 psPP for rates <500 Mbps <100 ps PP for rates <1.485 Gbps
  • Low power; 850 mW with all outputs active
  • Fast output edge speeds: 250 ps

  • Applications

  • Routing switchers
  • Production switchers
  • Master control switchers
  • Telecom/datacom switchers
  • Storage Area Network (SAM)
  • Packet switching
  • ATM SONET
  • Datasheets
    TitleSizeDateOther
    Language
    CLC018 8 x 8 Digital Crosspoint Switch, 1.485 Gbps667
    Kbytes
    4-Aug-06日本語  


    Other Technical Documents
    TitleTypeDate
    Use Video Standards for Eye-Opening Data Transmission: Mega-bits @ Many MetersApp Note 1999-12-29
    Broadcast Video Owner's ManualDesign Guide 2006-11-17

    Obsolete Versions
    Obsolete PartAlternate Part or SupplierSourceLast Time Buy Date
    CLC018AJVJQ
    DS25CP104A
    NATIONAL SEMICONDUCTOR
    30 Nov 2009
    CLC018PCASM
    NONE
    NONE
    03 Sep 2002

    [Information as of 9-Feb-2012]