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Advantages and Pitfalls of Using Fractional N Plls

SLIDE:          Advantages and Pitfalls of Using Fractional N Plls

Hello, my name is Dean Banerjee with National Semiconductor. I’m the applications engineer here and I’ve had a lot of opportunity to work with many of our exciting PLLs and also see some of our competitors’ PLLs.

Today we’re going to talk about the advantages and pitfalls of using fractional PLLs. I think a lot of the literature has a tendency to stress the advantages and the theoretical benefits. A lot of the pitfalls are in the implementation of the actual PLLs.

SLIDE:          Overview

Here’s an overview of what we’re going to talk about. The first thing is we’re going to talk about structural differences between integer and fractional PLLs. Then we’ll talk about some of the performance differences and then we can talk a little bit -- maybe about some of the competition and also talk about some of the questions you might have. So let’s go ahead and get started with integer N PLL.

SLIDE:          Integer N Example

So here’s our integer N PLL. Now, the way we start is we start with a 10 MHz crystal reference. It doesn’t have to be 10 MHz but just for this example we’re going to make it 10. I’m going to refer to this example or variations of this throughout the presentation. Now the 10 MHz was divided by 50 in this example, which is the R counter value to a comparison frequency of 200 KHz. Now we also have the output of VCO which is running in this case at 900.2 MHz which is the desired frequency. Now this 900.2 MHz is divided by the N divider, in this case 4501, which also gives 200 KHz. Now the block there that says Kf, the blue block, that’s the phase comparator and what that does, a phase detector, and what that does is it compares the two signals. If the two signals are the same then it outputs no correction. If the output frequency is higher than the part after divided by N is also higher then it will put out a negative correction and reduce the voltage to VCO which will, in turn, reduce the output frequency. If it’s too low then you’re going to see -- you’re going to see the opposite the charge pump will source the current. So basically what this device does is steer the control voltage around, such as the VCOs at their desired frequency. Now the 10 MHz crystal reference or whatever crystal your reference uses is typically fixed, it’s always fixed, and the R divider is usually programmable. It’s in the silicon or chip you’re using. The N divider is typically programmable. Now in the application the R divider is usually what you fix and the N counter you would change. So for instance if I want to go to 900.4 MHz I’d change that to 4502 and then the PLL would steer the control voltage such that the VCO was at 900.4 MHz.

Now there’s some terminology we need to introduce. The channel spacing is basically the increment you see in this case because 200 KHz is the frequency at the phase detector, that’s my tuning increment. If I can change the N by 1 I can increase or decrease my output by 200 KHz so in this case it’s -- channel spacing is 200 KHz. The output frequency is the 900.2 MHz.

SLIDE:          Fractional N Example

Now let’s go on to fractional slide so here’s where we are in our presentation. We talked about integer PLLs, now I’m going to talk about fractional PLLs. I’m going to show you the exact same example except for it’s going to be a fractional.

Okay, so now let’s look at the fractional N example. Here we have that same crystal frequency and the same output frequency but now that 200 KHz compare frequency has been increased to 1 MHz or 1000 KHz. Note that the tuning increment is still 200 KHz. In this case we have a fraction of one-fifth. This is a fractional N PLL. In the previous slide the N divider was restricted to integer values. In fractional PLL it can be a fraction and the advantage of that is I can raise this comparison frequency, by the way, is that 1000 KHz going to the phase detector. By raising the comparison frequency I’m also reducing the N counter value. So what benefit is that? The benefit of that is that the N counter value is lower and therefore the noise is less. Also, you theoretically have sidebands, spurious tones and sidebands which would be at this comparison frequency, in this case, 1000 KHz, the other case, 200 KHz. So, remember, the difference between comparison frequency and channel spacing. In this case the channel spacing is still 200 KHz because that is my tuning resolution. I’m assuming that denominator of one-fifth could be two-fifths, three-fifths, four-fifths, so that it sets the tuning resolution but my comparison frequency is a frequency presented to the phase detector, which is 1000 KHz.

SLIDE:          Fractional N Implementation

Okay, now in the theory the fractional N looks like such a wonderful idea and it is a good idea but there is a lot to say about the implementation that we really should talk about. You know, how does this example get 900.2 out of this integer divider? It uses a technique called fractional N averaging. So basically what it’s going to do is modulate this divider value around such that the average value is 900.2 MHz. So the first time it will divide by 900, the second time 900, third time 900, fourth time 900, and then the fifth time 901. The basic effect of this is that the average value is 900.2. Now there is going to be an instantaneous error which is actually much better illustrated on this slide.

SLIDE:          The Need for Compensation

Okay. This shows the need for compensation. So basically what this slide is showing is the blue line is the output of the theoretical divider. So if I have a 900.2 MHz output frequency and I divide by 900.2, I get 1 microsecond or 1 microsecond. That’s the ideal achieved value. However, that’s not what -- that’s not what the actual divider is doing. The actual divider is dividing by 900 the first four times and then by 901. So what’s going to happen is even though on the average I have the same number of clocked cycles there, there’s an error, a phase error. So after 1 microsecond the first divider would be correct but the other one, if you divide by 900 instead of 900.2 you’re actually going to have a frequency slightly higher than the desired frequency and that’s why you see the red line, the first one after right at 1 microsecond, it’s actually weaning by a phase error of epsilon. So what you know, how do I calculate this epsilon? If you look at the period of the VCO signal that would be 1 divided by 900.2 MHz. Now for the desired divider which actually has a fractional capability you would just take 900 two times, point two times that. For the actual divider we have it only takes 900 times that so that’s where you see the 900.2 minus 900 that’s where that numerator comes from. So you can also think of this as being off by two-tenths of a cycle. Now after the second time you divide by 900 this phase error is going to accumulate so now the phase error is 2 epsilon, after the third time, 3 epsilon, four time 4 epsilon, but in the fifth time after that I divide by 901 as opposed to 900 and so what this does is that this will increase the period of the red signal and the amount of that phase change is actually going to cancel with the first four. So in other words we’ve got the correct frequency and if I was to just do a fractional N PLL this way it would work. I would be able to see the output spectrum and it would have improved phase noise and things. However, the drawback of this is if it’s just phased away it’s going to cause a instantaneous phase error and this is going to result in fractional spur.

Now what fractional spur is, is that even though in the fractional case our compare frequency was 1000 KHz because my fraction is one-fifth I’m also going to see spur at 200 KHz which is exactly where the integer PLL would also have the fractional spur. If I change the fraction around, say from one-fifth to two-fifths, this value of this spur will change around. In this case this fraction is one-fifth. In some cases -- I could think of other cases perhaps if I have a fraction of four-eighths, for instance, you’re not going to see all the fractional spurs present. But for most of the time when I talk about the fractional spur I’m assuming that the numerator is one unless otherwise stated.

SLIDE:          Fractional Compensation

Let’s go to the next slide. So before we talked about the phase delay or phase error. So, how do you deal with this phase error because these fractional spurs, if you don’t compensate them, tend to be quite high? The most intuitive method is to use a delay compensation. Because we had phase error in the first slide of epsilon and then 2 epsilon and so on basically all you do is you add a phase delay which is equal to that phase error and therefore cancels this out. Now the good thing about the delay compensation, it certainly reduces the fractional spur and it is reasonably predictable. It’s not perfect but it’s reasonably predictable over process to some degree. It’s pretty stable over temperature but it does have a tendency to add phase noise and it can add quite a bit. Now with a fractional part, with the delay type of compensation, yes you have added phase noises due to this delay compensation, however, you have a benefit from having the lower N counter value and in any fractional PLL I’ve ever seen you usually end up with -- almost always end up with a net benefit in phase noise.

Now, there’s another method of compensation called current compensation. Now in the current compensation the idea is you go ahead and you let this phase error get to the phase detector. At the phase detector it’s going to put out some current that’s incorrect. So basically current compensation, you cancel this current with another current in the opposite direction and basically eliminate that. Method 1 and 2 if you do perfectly will have no fractional spur. In the current compensation method it tends not to add as much phase noise as method 1, delay compensation, however, these spurs tend to be more difficult, they manage over temperature so either one, method 1 and method 2, have their shortcomings and also you have to remember these techniques are analogs. So a new buzzword in fractional N PLLs now is Sigma Delta and Sigma Delta means that instead of using this analog type of compensation I use digital compensation.

SLIDE:          Overview

Let’s go to the next slide. So just to make sure everybody knows where we are we’re talking about the differences between integer and fractional PLL structure and now we’re going to talk about Sigma Delta PLLs and how do they work.

SLIDE:          SD Fractional Compensation

Okay. This slide shows a Sigma Delta modulator, a Sigma Delta type of compensation. Now if you think about the previous example we’re alternating between 900 MHz and 901 MHz. So I can view this as the N counter being fixed at 900 and then I’m either adding an extra count or not adding an extra count. That’s the first order modulator. That’s what we’ve talked about before. So you know you could just as well alternate between more than two values. You could, for instance, the zero and plus 1 would mean that, for the example, would be zero, zero, zero, zero and the last time 1. Zero, zero, zero, zero, 1. Every fifth time you’d put a 1. That would be first order modulator.

Now second order modulator would mean that I can alternate between four values. So instead of 900, 901, I’d do 998, 999, 900, 901. Now I might not use those exact same values. I can use any combination of those values. I can mix up those values. If I mix up those values, that’s actually called dithering and the basic idea here is to reduce the periodicity of the signal and that’s the reason for doing the Sigma Delta compensation.

Third order modulator just means that I can alternate between minus the four values, less than three values greater. So that would mean I could go -- alternate between values between 896 and 903 so we can alternate between more values. So the net effect of this is to push the spur energy out to the higher frequencies.

SLIDE:          1 Minute Z Transform Course

Okay. Now what does this slide have anything to do with Sigma Delta? That’s probably what you’re thinking. Actually, it has a lot to do with Sigma Delta. Any time you see any paper on Sigma Delta you’re always going to see these Z minus 1 all over the place. So I think it probably makes sense to do a quick Z transform class. So the idea of the Z transform is similar to the Laplace transform and it’s not exactly the same as Laplace transform but a simplified way of thinking about it is some discrete version of the Laplace transform N goes zero, one, two, three so this is discrete values. In the case of PLL we’re talking about -- we’re talking about clock delays so the first lesson in Z transform is that whenever you see Z minus 1 this means I’m delaying my signal by one clock delay.

SLIDE:          Accumulator In The Z Domain

So let’s do a little practice problem here. This is the accumulator in the Z domain so X sub Z is the input and the idea here is that I add the value -- the previous values in the (inaudible) so basically if I look at that output, Y of Z and then I see Z minus 1, that means I take whatever the output was before and I add it to the current value. So the effect of the if you solve your difference equation, basically all it’s doing is summing up the values. So this is what an accumulator looks like in Z domain. If you use a standard control theory where you say output is G over 1 plus GH and you do that math, you get this expression; Y sub Z equals X sub Z over 1 minus Z to a negative 1. I just wanted to show this is because you’re going to see this come up somewhere else in another slide. Now, this is not really what an accumulator does in a PLL because technically the fractional PLL also has a hard-limiting or hard-limiting timeout function. For instance, what the accumulator does is it tells you when am I going add one or not add one.

Let’s go back to that example when it was going between 900 and 900 and 900, 900, 901. How does it know when to add this -- add one and not to add one? This is called the accumulator and basically what you do is you take the phase error after every single event and you add it up and once it gets to one or greater then you output a one out of the accumulator and then you reset -- then you subtract one and you keep on going. So accumulator is like a summer except for once the value exceeds one it resets back to zero and then it puts an overflow bit which is used to add one to the N counter, that’s an accumulator in the Z domain.

So this is a Sigma Delta noise shaping compensation and really what this is, is this is an accumulator and this is actually a trivial case of a Sigma Delta PLL. In this case you see that 1 over 1 minus Z minus 1. That’s that summation function and then I hard-limit it. What this means is that if this function is .4 cycles then after it goes through this limiter it’s going to basically be zero -- or threshold is probably a better word. It’s going to be zero. If it’s 1.3, then it’s going to go ahead and go through. So basically, the output Y of Z is going to be some sequence of zeros and a one.

SLIDE:          SD Noise Shaping Equations

Okay. So let’s go to the next slide. So this is the Sigma Delta noise shaping equation for the first order modulator. A trivial case, but if we take that previous slide and we look at the output we see the output, we see the output Y of Z is X of Z times -Y sub Z and there’s a little missing factor here, but basically if we solve this transfer function you’re going to find out this Y sub Z equals X of Z times E times 1 minus Z minus 1. What does that mean in layman’s terms? That means the output signal is equal to the input signal times this quantization error but it’s got this finite difference.

SLIDE:          SD Fractional Compensation

Let’s go back to this slide just once again just to clarify we know what we’re talking about. So remember, Y sub Z is that output and we’re going -- if you look at that we take the previous output of the accumulator, which is zero over 1, so if there’s an overflow bit what it does is subtract it from the sum. So you can show that this is the action of the accumulator.

Now you look at this E sub Z, you know, what is -- what is this quantization noise? What does it mean? You know, basically, if we remember that slide when we were showing the -- we were showing the phase error of epsilon, 2 epsilon, 3 epsilon, what does -- a way of viewing this is, is assuming it’s playing the game assuming that the divider is ideal and then you have this undesired quantization noise and in the previous example with epsilon, 2 epsilon and so on. So you’re viewing this phase error as some sort of quantization noise.

SLIDE:          SD NOise Shaping Equations

So now let’s get back to the slide we were on already. So, we’ve already gone through worked up transfer function and we see when we work it out we see two pieces, X sub Z which is the divider signal, but then we see this 1 minus Z minus 1 and what this is, is a finite difference. So this is the discrete analogy of the -- discrete analogy of a derivative. You’re taking whatever the error was in this clock cycle; subtract what it was in the previous clock cycle. So that’s a finite difference. It’s sort of like a derivative or you can think of pushing the low frequency energy to high frequency energy.

SLIDE:          High Order SD Modulators

So, let me show you what this looks like in the the frequency domain. So this particular slide shows you what the effect is. Now it’s not drawn to scale and that Fcomp over 2, that’s our comparison frequency. Remember in this example was 1 MHz or 1000 KHz. So, basically the spur energy theoretically below that frequency is pushed out to higher frequencies. For the first order modular you see that there is some shaping but not as much as for higher order modulators so the higher order modulator is better. However, there are drawbacks. One of the things you have to realize is if you’re pushing this energy to higher frequencies you need to filter better at higher frequencies. The whole concept is a loop filter is able to filter this high-energy frequency. If you think of comparison frequency over two, in this case 1 MHz divided by 2 is 500 KHz, that’s really pretty far away from the carrier so you would think that that would be easy to filter but you really need to have your filter roll-off at a faster rate than this image is pushing the noise out. Practically speaking if you violate this assumption, loop filter order equals sigma delta order plus 1, if you violate that it depends upon the situation. If you have a wide loop bandwidth then you’re going to see a sub fractional or bonus spur so in this case you have a spur at 200 KHz, which is our fractional spur but you can also with Sigma Delta PLL you can get things at sub fractions of that for instance, at 100 KHz and even 50 KHz. It depends on the modulator. For a third order modulator you can get at half is very common, is what I’ve seen in some of the things I’ve tested. But the concept is to basically push this spur energy out to higher frequencies and then at the higher frequency offset you can filter better.

Q. So we have a question here. The question is, how do I know what order modulator and PLL -- what order modulator my PLL chip is using and does it change with the fractional order?

A. So, you know, the modulator of the Sigma Delta PLL is fixed for the application. A lot of Sigma Delta PLLs have a fixed modulator. In general the first order Sigma Delta modulator is considered a trivial case and people do not typically call a first order Sigma Delta PLL a Sigma Delta PLL, they just call it a fractional PLL so almost always it’s at least second order. There’s also parts on the market today with third order and even fourth order modulators or even selectable between the different orders of modulators. There’s definitely trade-offs between what order you use. If you use the higher order modulator it might improve your spur level at the -- at the traditional fractional frequency, for instance in this case my fraction is one-fifth and power frequency is 1 MHz. Traditional fractional spurs should be 200 KHz so you might actually improve that but then it might give rise to other fractional spurs at -- at other offsets like 100 KHz and -- and at different offsets so there’s a tradeoff involved with the modulator order.

Q. Let’s see. We have another question. What about dithering?

A. Dithering is basically when you take the sequence and you mix it up. For instance, in the first order modulator we did 900, 900, 900, 900, 901 so we could represent that as -- if we take off the 900 just go zero, zero, zero, zero, one, dithering means that I can mix it up a little bit and the first time I put the one in the fifth time and maybe the second time we do it the fourth time, third time, third time, second time and I mix it up a little bit and what that does is decrease the periodicity of the signal. In general, in practice what that seems to do is for the main fractional spur it doesn’t seem to do a whole lot, maybe a little bit on the -- but for some of these sub fractional spurs it seems to help them quite a bit. And actually dithering, some parts actually have dithering where you can turn it on and turn it off and in some cases dithering, especially when you have a fractional numerator of zero, can give rise to spurs that would otherwise not be there.

SLIDE:          3rd Order Modulator Structure

Let’s go to the next slide. So this is a third order modulator and the whole point of this is just to show that you can cascade multiple first order modulators and make third order modulators. This architecture -- architecture can change from PLL to PLL so I don’t want to focus too much on that but what you see here is this 1 minus Z minus 1 term, that high pass filtering term has a cube term here instead of 1. So what that does is increase this noise shaping capability.

SLIDE:          DS Filtering Example

So, let’s go look at the next slide which is a Sigma Delta filtering example. So here I’ve taken a noise source and no other better noise source then the stock price of National. This slide was made, obviously, when the stock price was a little higher than it is today, but if you notice and you look at the price, the blue line, you see that there is this general rising positive tendency there. I know it gets from 40 to 22 but after that you see this rising tendency and then you see a little dip at the end but if you ignore those at the beginning and end you do see this rising tendency which is a low frequency type of signal. Now if you look at the pink, which is a first order modulator, the first thing you notice is the DC component is completely gone. Then notice that whenever there’s a big change in National stock you see bigger changes. You also notice that low frequency, that gradual rising tendency is gone from first order modulator. Third order modulator exaggerates this action the lower frequency is hard to see but the lower frequency terms are actually even less and every time there’s a change in National stock prices this change is exaggerated even more. So that’s just illustrating to you what that would look like.

SLIDE:          Theoretical Fractional N Benefits

Okay. So now we’ve talked about some of the architecture, integers, fractional PLL, Sigma Delta, now let’s talk about some of the performance differences. Let’s first talk about some of the textbook benefit for fractional N. Now when the fractional N PLLs first came out I spoke to many customers who were very excited about them and really believed they’re going to be so much better and there are applications and times when they’re better. But these advantages are probably a little bit on the optimistic side. So in terms of silence or phase noise the theoretical improvement you get a 20 log N because the N value is less, but then the phase detector becomes be noisy and the net improvement is a 10 log N so if I reduce my N count by a factor of 5 for instance, that’s a theoretical 7 dB N improvement. That’s theoretically the benefit. Now the spurs theoretically you would think you don’t even talk about fractional spur and you just say, this spur is five times further out and easier to filter but as we see there are fractional spurs so you know that that’s a theoretical benefit only.

Now for switching the idea is, if the spurs are lower you can afford to make the loop bandwidth wider and improve your lock time. The loop bandwidth of your PLL system dictates the lock time so if you have a narrow loop bandwidth, you have lower spurs but then the switching time is much faster -- I’m sorry, the switching time is much slower. If you open loop bandwidth to make wider, the spurs go up but then switching time is faster. So the spurs is one of the restrictions whatever your requirement of the spur is one of the things that puts limitations on your switching time. In some of these situations the spurs are not a limiting factor at all and there’s another restriction that comes in that’s that your loop bandwidth can’t be much greater than one-tenth of your compare frequency and that’s another restriction that fractional N PLLs can help avoid. So theoretically there’s definitely benefits.

SLIDE:          Phase Noise Potential Comparison

Let’s talk about some of these benefits. The first one is phase noise. Now this -- this particular slide has various National PLLs and it’s basically all these parts were tested at a few points and then the data curve was extrapolated from that. So if you look at the green curve which is 2326, 2310 and those ones, all those green ones are integer N PLLs. The blue one is fractional PLL. Now on the Y-axis is the phase noise, now X-axis isn’t labeled, but what that is, is channel spacing, not to be confused with comparison frequency. So in the case that we have the channel spacing is 200 KHz and the comparison frequency is 1 MHz. So in this chart it would be 200 KHz. Now the benefit of fractional N comes from raising the comparison frequency but there’s limitations. The N counter has legal divide ratios that you can’t violate so you can’t do that. Some phase detectors have all phase detectors will have a maximum frequency. You can’t violate that. It’s difficult to go above what the crystal frequency is unless there’s a doubler on the chips. So these are just some of the practical limitations of that. But this assumes that there are none of those limitations and just shows you the general trend. You see when the channel spacing is very small the integer parts, which are all the green curves, are all higher and the fractional parts are much better.

Now notice that one of the interesting curves here is 2346 which is actually one of our newer integer PLLs with very low phase noise and compare that to 2354 and you can see that actually around 100 KHz it looks like it’s actually better phase noise which is true. What happens is with the fractional parts is the compensation adds the phase noise. So if you have a high comparison frequency already, then the benefit of using the fractional PLL is not as great. The 2354’s are maybe second generation, 2364 we just released.

Now you’re going to see this mystery part, LMX****. I can’t tell you the part name but I can tell you it’s a very real part, fully evaluated part, it’s a Sigma Delta part, excellent performance and you see that the phase noise around there is minus 99 or so. And this is, I think, a fixed 1 GHz output frequency and there’s other factors like this assumes a 4 KHz offset frequency. If I chose an offset frequency which is farther all those fractional PLLs where you see the curves start to flatten out they wouldn’t flatten out the same way because this is really the effect of this 1 over F noise is what you’re seeing. So the point of this slide is when you have a narrow channel spacing, fractional PLL provides the most benefit.

SLIDE:          Spur Comparison

Let’s look at the at the spurs. So on the spurs we see, again, when the channel spacing is narrow the fractional PLL outperforms. In the immediate range there like 100, 200 KHz it sort of depends which part you’re talking about, and at higher frequencies this is basically extrapolated from data. I haven’t really done much comparison past the megahertz of fractional PLLs but theoretically they seem to be better. This is 1 GHz output frequency and you see the channel spacing varies. At the low frequencies what happens with the integer PLLs is the leakage of the charge pump is the dominant factor. Then at high frequencies, the mismatch is the dominant factor. For fractional PLLs generally they’re basically immune to leakage of the charge pump. It has some effect, but it’s very, very little. In integer PLLs it’s a much greater effect. So, and again, the green curve is the integer PLL; the blue is the fractional PLL. So that’s one of the things of the fractional PLL, low compare frequency seems better. There’s an intermediate range where there the integer PLLs seem to be about the same.

SLIDE:          Fractional Spur Games

Let’s go to the next slide. On the subject of fractional spurs we have something called a fractional spur game and what this means is that if you can avoid, for instance, if your numerator is -- if your denominator is 100, so fraction 1 over 100, that’s going to be the worse case of that first fractional spur. If you can avoid that, for instance 2 over 100 or even 3 over 100, if you can avoid that 1 over 100 and also 99 over 100, you’re going to have lower spurs and it will result in a spur improvement. This case, it usually happens in CDMA and a lot of parts have a denominator of 1968 which conveniently divides into the 19.68 MHz crystal. In this case you have a very large denominator but if your numerator changes -- if you never have to use the numerator of 1 or 1967, then you get a spur benefit. In fact, if you never have to use the numerator less than 7 or anything close to 1968, you get a benefit. So, again, this is something that happens when you’re tuning resolution you can actually achieve with a PLL is better than what you need for the application then CDMA is the notable case where this happens.

This particular slide shows the fractional spurs of the 2364. This for this example, the compensation was turned off and the only reason for this is just to make the numbers more consistent, easy to see, it doesn’t add that much variation but a little bit and also just to make the spurs easier to measure with the automated test equipment. And I think, even though the 2364 is a specific PLL you could probably assume that any fractional PLL with the compensation shutoff, I wouldn’t be surprised if it looked very similar to this. Again, this has spurs outside the loop bandwidth so I don’t quite remember what loop bandwidth is, but the point we’re trying to make is that, again, that 1 over 100 and 99 over 100, the worse case spurs are there. If I could avoid that, then I get a 10 dB N improvement and I get 28.2 and I think that’s that enumerator of 33 and 67, I believe. But if can avoid those, I still get another benefit so this gain is most apparent when you have a really large denominator and you can really get some improvement out of that and the most the most visible case is in is in CDMA.

Q. I have a question here about how we can get a soft copy of the presentation.

A. This is going to be archived on the website on Yahoo so you don’t need to worry about that. Or you can get it through National’s website as well.

SLIDE:          Lock Time

Let’s talk about lock time of fractional N PLLs. In the theoretical books they say that the fractional PLL has faster lock time. Reason for this there’s two restrictions. One is that if you’re in the situation where you want a loop bandwidth wider than one-tenth of your comparison frequency that’s a limitation, then the fractional N PLL allows the wider loop bandwidth because it has a higher compare frequency. Now, there’s also the thing about the fractional spurs which if they’re lower give you some benefit. It’s hard to really say which is lower fractional spur, integers spur and it really depends upon which fractional part, which integer part.

SLIDE:          Lock Time

But there’s also another thing called cycle slipping. You know if your compare frequency is 100 times your loop bandwidth or less what this means is you could probably model the lock time quite well with just pulls and zeros and Laplace transforms and things like that and never even worry about the fact that there’s a discrete action or a phase detector. If you do that the simulation tends to turn out pretty fair. However, when the comparison frequency exceeds 100 times the loop bandwidth or in that ballpark, and that’s just a round number it’s not an exact number, you get this phenomena called cycle slipping. It’s actually easier to show cycle slipping then to talk about it with words.

SLIDE:          The Impact of Cycle Slipping

Now this particular slide, what we’re showing is cycle slipping. I have the exact same loop bandwidth, in this case 2 KHz, and my frequencies when switching from 898 to 915 MHz. So basically this is just a simulation but the simulations seem to have some reasonable agreement with the real world results. Now if you notice when the compare frequency is 200 KHz the lock time matches the analog and the analog is the one done with poles and zeros in a Laplace transformer. These ones where done by numerical approximation and considering the action of the phase detectors. Now when you do compare frequency of 1 MHz you see that this lock time is increased and if you look at the edge rate it looks like a analogous thing to use is slew rate of an OP AMP, you see that it gets less and less as the compare frequency gets higher. With the 1 MHz that would be 1 MHz over 50 so that’s probably about 500 times loop bandwidth. You see that the cycle slipping is reducing your or increasing your lock time. By 2 MHz it’s really impacting. This is really relevant, especially some of these Sigma Delta PLLs have very, very high fractional denominator. You can raise your compare frequency very, very high and it becomes a very real issue. Now the net effect on this lock time, to know what the lock time is you’d have to look at 915 MHz and stand in very close but just as a ballpark estimate type of thing, if you look at the time it takes to reach that peak you can see that time is increasing. Maybe the first case, I mean analog and 200 KHz, that looks about maybe 250 microseconds or so. When I had the blue one with 1 MHz this guy looks closer to 800 microseconds so you can take the difference in the peak time and that gives you an approximation of how much that’s going to hurt your lock time.

SLIDE:          LMX247X Cycle Slip Reduction Circuitry Example

So here we have that mystery part again that I can’t tell you the part number yet but I can say it’s very real and a wonderful product and you’ll hear about it very soon. It has a cycle slip reduction circuitry which effectively decreases compare frequency and increases charge pump current but keeps the same loop bandwidth and you can see in this example with actual measured silicon that the peak time is being decreased from 561 microsecond to 151 microsecond so you see it’s a good decrease in the lock time and that difference between 834 minus 46 is approximately 561 minus 151. Not exactly, but as a quick approximation, it’s true.

So let’s talk about some of the advantages and disadvantages of fractional N versus Integer N. The advantages of the fractional N I think in just about every case has got better phase noise. In particular, Sigma Delta parts I don’t think there’s any question that the phase noise is better. In some applications when the fractionality is very high you can play fractional spur games which make it pretend your spur is potentially lower. I’ve seen some very bold claims on many data sheets, especially Sigma Delta PLLs for very low spurs but then when you come and you look at silicon you’re like, how do they get this claim and the claims are coming most likely because they’re not considering a numerator of one. Now that might, at first, seem like a marketing trick but if you really don’t have to go to that frequency then it’s more then a trick, it’s a method. In fractional PLLs they’re best optimized for things of narrow channel spacing. Anything below 100 KHz I think I would consider narrow. Now the example I had had 200 KHz and to be honest with you that’s a bad example for a fractional PLL. The reason I chose that is because it had a simple number of one-fifth and made some numbers look nice but in general, you know, fractional PLLs have much higher modulators than 5.

What are the pitfalls? One is for the cycle slipping. The cycle slipping is what increases your lock time and that’s what that’s an artifact of having this higher compare frequency. They’re also more difficult to use. A lot of these parts have different controls and things. In particular Sigma Delta parts many bits and things to play with, we would trade off phase noise for spurs.

SLIDE:          Fractional N VS. Integer N

Okay. So we’ve already talked about integer, fractional let’s go to the next slide here. Here we go. That’s the slide I was looking for. Now we have the conclusion. So the most benefit for applications with narrow channel spacings. With narrow channel spacings I can clearly say fractional spurs are better because the integer parts have the charge pump leakage, begins to dominate and especially when you consider the spurs over temperature. Leakage current typically doubles for every 10 degrees increasing current so you mean that room temperature of integers first (inaudible) channel spacings they can be quite hideous at higher temperature or for that matter humidity can also increase the leakage on your board which effectively makes these spurs worse. The Sigma Delta PLLs deliver excellent performance. What do we mean by that? In particular I think phase noise, there’s no question that the phase noise is drastically better no matter who’s Sigma Delta parts you use, phase noise is definitely better compared to integer or compared to a traditional fractional PLL.

I encourage you to look at National’s PLL offering. We have parts the with the low spurs, excellent phase noise and the faster lock times due to the cycle slip reduction and fastlock. We have a lot of new parts coming out that have circuitries to deal with cycle slip and also fastlock, it’s more of a benefit to for the integer PLLs. And encourage you to check out Wireless.National.com for all your PLL and wireless needs. We have data sheets up there, application notes, simulation tools of these PLLs up there. It is actually quite good all-in-one site.

Q&A Session

So, anyway, now I think we’re ready for some survey and some questions. So if you would, I’m ready to take some questions here.

Oh, okay. Let me go let me go back to one of these questions here I have. Questions on this phase noise potential.

Q. Okay this question is why is the 2346 outperforming the 2354? Does it’s the fractional PLLs have the better phase noise?

A. And if you look at the 2346, that’s that dark green curve and 2354 is the light blue and you’ll see that at some cases it’s actually outperforming. The 2346 is designed for low phase noise and the advantage at the higher compare frequency is you don’t have to worry about the added noise due to the compensation circuitry. So it’s the compensation circuitry that’s making the difference. At the lower compare frequencies -- I’m sorry, lower channel spacings, the 54 is more on par because it has the advantage of the lower N value to deal with.

Q. What’s our next question? Okay. It says, which parameters as well as phase noise and reference spurs must be taken in account to estimate the charge pump current?
A. I’m not quite sure if I understand the question. I mean, the charge pump current is something you read from the datasheet and you get that from there. If the question is saying, what is the charge pump current that I should design for, now that does have an impact on some of these performance parameters? For instance, if I have a PLL I could chose to design for a -- say a 1 milliamp mode or a 400 milliamp mode and many PLLs have many different selections for charge pump current and in general, the highest charge pump current always gives the best phase noise. In terms of spurs, the current really doesn’t make a difference. Now if you just sit there and change the current and don’t change your loop filter then you will see the spurs change. But if you redesign your loop filter, what you’re going to find is that the spurs are pretty much the same. However, if you redesign your loop filter you will find that the charge pump current is that the higher charge pump current has better phase noise and it depends upon which PLL, you know, how much difference that phase noise can be. It can make anywhere from less than 1 dB to 4 dBs.
Q. Okay. I have another one. Can you please explain slide 25? It did not come over.
A. Well, this is my slide. This is my slide 25. I hope this is the right one. This is the one we were talking about cycle slipping and the loop bandwidth is designed and redesigned for the same loop bandwidth but all I’m doing is raising the compare frequency and I’m seeing that this discrete action of the phase detector is increasing my lock time so that’s the cycle slipping for you.
Q. Next question. How can you protect the spurs with very high modular counters?
A. In general, the Sigma Delta PLLs in general have very, very high modulators and typically I’ve seen numbers 2 to the 23 or 220 through minus 1, very large numbers that would be really, really high. It can very fine frequency resolution.

Now the way to deal with fractional spurs is to first think about the uncompensated, traditional fractional PLL because this case you can actually predict pretty well. In the case of an uncompensated fractional PLL and if the numerator is 1 you can take the number 1.6 dB and then that would be theoretically inside the loop bandwidth. Then you look at how much the loop bandwidth rolls it off and that would tell you your new spur level. Now the way to treat any sort of analog compensation, you would say, okay now the compensation improves it say another 20 dB or whatever that is. Now for Sigma Delta PLLs you can use a similar model except for it’s a little more tricky because the in band spur does not completely track that close-looped transfer function and the reason is because, you remember this noise shaping, it has a slope to that so what you’re going find out is that if you use that method you’re going to find out that the farther out the fractional spurs have a tendency to the actual measured ones tend to be higher than the prediction if you don’t that into account.

Q. Please explain the difference between comparison frequency and channel spacing. That’s our next question.
A. Comparison frequency is the frequency presented to the phase detector. Now in the case of this example we need to tune every 200 KHz, so that’s my channel spacing and how I achieve that channel spacing is irrelevant, it’s still the channel spacing.

Let’s go to my fractional slide to show the difference here if I can find. But in the case of a fractional PLL you’re able to achieve a better resolution because the N counter is able to tune into fractions.

Here comes, here comes the slide now. So in this case my compare frequency is the 1 MHz because that’s the frequency presented to the phase detector but my channel spacing is still 200 KHz because I can do 900 in zero-fifths, 900 to one-fifth, 900 to two-fifth, so I can change in increments of 200 KHz.

Q. Next question. Do typical available integer PLLs all suffer from cycles at the higher comparison frequency or do some have cycle slip compensation?
A. Now, my bias is toward National Semiconductor because I work for National Semiconductor and have access to parts and things like that but in general integer parts don’t have much of a problem with cycle slipping in most applications although you can certainly have it. It has nothing to do with the fractional compensation or anything but usually what happens a compare frequency is low enough you don’t deal with it. So there’s technically is not something intended to stop cycle slipping for integer parts. Now if you design for 10 (inaudible), yes you can see cycle slipping.

We do have a feature called FastLock which basically what that does is increase the charge pump current and switch in a resistor and the impact of that is increase the loop bandwidth which because the loop bandwidth is wider the cycle slipping is reduced so for an integer PLL just traditional FastLock is a good method to fight cycle slipping. In a fractional PLL the issue with the FastLock is -- you know, FastLock is National’s routine, there’s several other routines but most of them involves increasing the charge pump current but if all you do is increase the charge pump current and potentially switch in a resistor or something like that this are theoretically designed for a second order filter.

In Sigma Delta PLLs often times you get pushed to higher and higher order filters and in that case it’s difficult to keep the thing optimized when you’re in the FastLock mode and also when you’re in the traditional non-FastLock mode. So the answer I guess the short answer to that is integer PLLs have traditional FastLock which also helps fight cycle slipping if it was a problem. The Sigma Delta PLLs as far as I know we’ve looked at several competitors’ parts which we consider to be major players and also this mystery part, LMX****. Our LMX****, of course, we have that slide on the cycle slipping where we have a circuitry for that. For these other competitors as I’ve seen, they do not have anything intended to really fight cycle slipping. They have might have a mode where you increase the current or something but again, that might be difficult to use with higher order filters.

Q. Ah. So we have another question. How you basically say you don’t understand how it’s possible to reduce the spur in the synthesizer so I guess that’s talking about compensation.

A. So let’s go back let’s go back to this slide here, The Need For Compensation and as we see that if we had perfect compensation there would be no such thing as a fractional spur but the problem is if you try to do a time delay you have to get the time delay correct. If the time delay is not correct you can add phase noise to fractional spur. If you do currents, you have to get the current matched to the right timing and the right magnitude of that current.

Okay let’s go ahead and put out the survey slide and you guys can work on the survey while we while we answer some more of these questions.
Q. Okay, let’s see. What is the cause of cycle slipping?
A. You know to actually explain the cause -- I guess it’s difficult and I always end up (inaudible) and circular logic trying to explain. I can certainly show you what it is; I’ve certainly seen it. I even wrote that simulation tool that models it but to actually tell you what’s going on basically what’s happening is that the the loop bandwidth or the PLL loop is not fast enough to correct for this change in it’s phase error so what happens is when you consider two signals and you say is this one, you know, is this one leading by 1 degree or 179 degrees lagging? This is the dilema when you close to this thing you can get in a situation where if you’re just a little bit off you can cause the charge pump to burp in the wrong direction and that’s sort of what’s going on. I know that’s a little wavy but that’s all I can do.

Q. Next question. When are you coming out with third addition of your PLL book?

A. I’ve always thought I was going to do that last year, then next year. For those who don’t know I’ve been supporting customers for National for quite awhile and what happened is I got so many questions I start writing documents to address that and after that the documents grew and grew and then I just sort of joined them together and called it a book and then I just self-published it myself. Right now there’s a second edition out at wireless.national.com I also have it on Amazon. There’s so much ammo for a third edition it’s not even funny with all these things about fractional spurs and Sigma Delta PLLs and cycle slipping. There’s quite a bit that’s not in there. It would be nice if I could have it released by the end of the year and I certainly have the material I just don’t know when I have the time but eventually I will release that.

Have anymore questions?

Q. How does this mystery LMX**** stack up to the competition?

A. Well, we have looked at actually three of our leading competitors and the marketing folks say it’s not nice to name names and point fingers at them so let me just tell you some of the general trends. In general of all of the parts, one of things I noticed is that these competitor parts don’t have the cycle slip reduction circuitry. They have the FastLock, but again, it’s difficult if you have a fourth order filter to just raise the current and keep everything optimized and a lot of times you do need higher order filters to take care of that. All Sigma Delta PLLs have outstanding phase noise. I think our fractional spurs in general are equal or better to whatever I’ve seen. In terms of phase noise I’ve seen some competitors are close, some were way better, some are even slightly better than us but I think that we really have a very competitive product if you consider the lock time and the spur. When it comes to phase noise the problem we’re having or I’ve been having a lot is characterizing these parts is that as phase noise is getting so low that it’s difficult to measure and difficult to keep the VCO noise from distorting your measurements.

Q. Next question. With many VCOs the control voltage is very high. Will an active filter decrease or decrease the phase noise versus a passive filter?
A. Okay, right. You know right now there’s a definite bias towards cell phone market and low-voltage applications but definitely in base stations or cable TV tuners, satellite tuners, the VCO requires a higher voltage then the PLL can supply, a classical problem. Our new our easy PLL actually we’ve just added support for active filters and you know, you can add an OP amp there to basically what that does is it increases the voltage so the best way or the way I’d recommend to do this is to design it such that the output of the charge pump is held at a constant voltage. This just gives you best spur performance. And then you can use this circuit that is shown on our wireless.national.com and it will increase this tuning voltage now.

But getting to your question, how does that impact the phase noise? That is something I would rather answer with a simulation tool which we have there online. The is basically what it is. The voltage noise to the OP amp modulates the VCO tuning in sort of a way – a similar way you would derive a classical spur, either you go through this vessel function and you consider at some fixed offset frequency, that’s how you model this phase noise added by the OP amp. In general the key specs on that are the low noise voltage or -- yes, low noise voltage and also the other thing you have to watch out for is some of them have very, very high bias currents and that can really raise your spurs.

Okay. Well, thank you so much for joining us. It’s been a pleasure. I hope you’ve had a good time. Thank you very much.

(END OF PRESENTATION)