SANTA CLARA, CALIF., August 17, 1995 --The Low Cost Flip Chip Consortium has signed a
$21,097,981 agreement with The Department of Defense's Advanced Research Projects
Agency (ARPA) to advance the technology and domestic production infrastructure for flip
chip assemblies of integrated circuits.
The agreement, led by National Semiconductor Corporation, is sponsored under the
Technology Reinvestment Project (TRP), is a cost share agreement. The U.S.
government's share of the project is $9,829,610. The balance is supplied by the
Consortium.
In addition to National Semiconductor, members of the Consortium include: Aptos Corp.,
Delco Electronica Corp., Hughes Missile Systems Company, Jabil Circuits, Litronic
Industries, Inc., Sheldahl, Inc., and SunDisk Corp.
The objective of this program is two-fold: to develop technologies and capabilities
necessary for the delivery of low-cost flip-chip assemblies and to establish the
manufacturing infrastructure to deliver end product. This initiative springs from the
growing recognition that both military and commercial electronic products are evolving
toward lower cost, smaller form factor, lower weight and higher performance which can
best be realized at the chip level by eliminating the IC package and transitioning from
perimeter to area I/O.
"Flip Chip assembly is projected to replace wire bonding as the predominant method of
connecting high performance, high pin-count integrated circuits as well as high volume
consumer products," said Jim Dunham, Packaging Program Manager for National
Semiconductor. "This technology will enable U.S. manufacturers to maintain the lead in IC
packaging and PC board assembly techniques."
According to Dr. Nick Naclerio, Prorgam Manager for the government thrust in low cost
electronic packaging, "The transition from perimeter wire bonding to area flip chip is one
of the most significant paradigm shifts which will take place in the IC packaging industry
in this decade. The Flip Chip Consortium is an integral part of the ARPA flip chip thrust
and will play a key role in developing a robust domestic infrastructure."
The team will address the complete delivery chain, from chip design and wafer fabrication
through wafer bumping, handling and shipping, to rapid prototyping and high volume
board assembly. The consortium will develop the processes, tools and cost modeling
approaches essential to establishing the infrastructure.
The end result of this two-year program will be: (a) the creation of domestic capabilities for
high-volume, low-cost solder bumping; (b) design rule sets and industry standards for area
array pad layouts and wafer bumping; (c) low- cost, fine-line substrates for bare die chip
attach; (d) flip-chip assembly processes and design rules for board attach of these chips;
and (e) reliability standards for environmental qualification.
In addition to the infrastructure processes, the Consortium will also generate new product
applications to serve both military and commercial markets which will demonstrate the
cost-effectiveness and reliability of the technology.
CORP95001TECH