Overcoming Impedance Discontinuities in High-Speed Signal Paths by Using LVDS
Brian Stearns, Principal Engineer

Figure 1. HD Video Router Diagram

At data rates from 400 Mbps to 1.5 Gbps, data signal paths become transmission lines. At these speeds the signal path model must include the reactive parasitic components in the cable or backplane. It is not just the data rate itself - the fast edge rates contain even higher frequency energy that react worse in distributed impedance environments. Ignoring parasitic impedances and impedance discontinuities above 200 Mbps will cause added noise in the transmission line, and data bit errors will occur.

Consider a basic High-Definition (HD) digital video router as an example of this challenge: HD video routers manage multiple HD source streams for distribution in broadcast, studio, or production video facilities. HD video channels operate from 270 Mbps up to 1.485 Gbps, demanding careful layout and consistent design practices to ensure the switching router system does not degrade the integrity of the video data.

In this system (Figure 1), an Adaptive Equalizer (EQ) receives the HD signal directly from the BNC connector. A common backplane connects the signals from the input card to the switch card for output to the desired destination channel. The signals travel point-to-point from the EQ across the PCB approximately 8 inches to the backplane connector, then across ~3 to 15 inches of backplane (depending on the slot used) to a second connector, then across another 8 inches of PCB to the inputs of the crosspoint switch device. A re-clocker/cable driver connects directly to the outputs of the crosspoint switch to drive the signals across cables. These HD video router systems are modular and may have anywhere from 8 to 1000 input/output channels. Therefore, signal density can be very high.

Figure 2. Example TDR Plot of Impedance Across the Signal Path (See Figure 1 for discontinuity locations)

The common FR4 circuit board materials are a consistent impedance environment, but the distributed parasitic impedances will have a negative effect on the signal quality. Most affected are the fast edge rates as a result of the numerous frequency components operating higher than the fundamental data rate, causing signal losses and sluggish transition times. In addition, all the interconnections between the components (such as the BNC connectors, integrated circuits, vias between board layers, or the connectors between boards) can cause impedance mismatches from the characteristic impedance (Z₀ ), which will also affect signal quality (Figure 2). The dense backplane connectors inductively load the signal path, while vias in the PCB capacitively load the signal path. Signal reflections will occur at any location along a transmission path where a change in impedance exists. These reflections and parasitic impedances will cause loss of signal amplitude, ringing, rise time degradation, and EMI.

Figure 3. Eye Pattern at Input to Crosspoint Switch After 31” of FR4

In this example system there can be up to 31 inches of FR4 from the EQ outputs to the input of the crosspoint switch, with several impedance discontinuities along the way. If the speed of the incident edge is 175 to 200 ps/inch down this path, and the data rate is 1.485 Gbps (half-wavelength = 343 ps), then there can be as many as 18 transitional edges on the path at any given time. Reflections caused by the incident edge at impedance mismatches will affect all the edges present on the signal path. Reflections from edges 1 through 17 will greatly distort edge number 18 by the time it arrives at the end of the signal path. The resulting eye pattern (Figure 3) shows the loss of amplitude, excessive jitter, and rise/fall time degradation.

One possible solution to this challenge is to use higher quality connectors between the daughter cards and the backplane. This will minimize the discontinuities of the connectors. Better via design will further flatten the TDR measurement plots so that the apparent impedance over the length of the signal path stays much closer to Z₀.

Figure 4. Buffer Locations to Overcome Impedance Discontinuities

Another, more cost-effective solution is to use a simple LVDS buffer, such as the DS90LV004, to drive and receive the signal across the backplane. This effectively breaks the transmission path into smaller segments to mask the impedance mismatch and diminish signal attenuation. Place a buffer at the edge of the daughter card to drive the connector and backplane, a second buffer on the switch daughter card to receive the signals (Figure 4), and re-drive them to the input of the crosspoint switch to effectively hide the impedance discontinuities between the two buffers (Figure 5). Proper terminations also ensure that the receiver absorbs all the energy in the line and none reflects back to the source.

Figure 5. Eye Pattern at the Crosspoint Input with DS90LV004 Buffers Isolating the Backplane Connections

In addition, the buffers typically offer additional signal quality enhancements to improve the original signal. For example, buffers featuring input equalization will remove the deterministic jitter from the media losses before delivery across the backplane. Output pre-emphasis can boost the amplitude of the signal, further opening the eye pattern at the crosspoint inputs or receiver. High ESD ratings on the buffer I/O protect the other components on the daughter cards from ESD events elsewhere on the backplane.

Summary

High-speed interfaces across backplanes require impedance control along the entire signal path. Using simple LVDS buffers to isolate impedance discontinuities or to shorten the interconnect lengths can reduce system costs and enhance the interface performance by eliminating the need for expensive high-frequency connectors.