Figure 6 shows the stable ESR range of the LP2982, which is a low-noise, high-performance LDO regulator. The first thing to notice is that it is a pretty wide range, with greater than 100X from minimum to maximum range value of stable boundaries. The stable zone is centered at around 1 Ohm, which matches very closely with the typical ESR of a Tantalum capacitor of this capacitance value. It would seem the stability limits for the output capacitor are pretty easy to meet, but users sometimes find ways to miss it.

The biggest reasons many LDO's oscillate are:

a) Using an aluminum electrolytic output capacitor in a design that operates at cold temperatures. Aluminum capacitors may have an ESR in the “stable” range at room temperature, but their ESR increases exponentially as the temperature goes below about 10 degrees Centigrade. These capacitors must never be used with LDO's if cold temperatures can occur in the application.

b) Using a ceramic output capacitor on an LDO not designed for it. The typical 2.2 - 4.7 uF ceramic capacitor will have an ESR of about 5 milli Ohms. This puts the ESR zero somewhere around 6 MHz where it clearly won't help compensate the loop. Using ceramics on the output of LDO's which are not designed to work with them is presently the #1 reason for unstable LDO operation.

Why most LDO's hate ceramic bypass capacitors

The last section explained why most LDO regulators will not operate in a stable mode with a ceramic output capacitor. Their loop requires the ESR of the output capacitor to supply a zero which gives the phase lead necessary to cancel out the effects of one of the low-frequency poles.... and ceramic capacitors have almost no ESR, so they won't provide any phase lead. Most LDO's designed in the late 1980's and early 1990's were made assuming a Tantalum capacitor would be used for the output capacitor, and so they don't tolerate ceramics very well.

But, there is another “ceramic” oscillation mode so sneaky it deserves it's own section: suppose the LDO has a perfectly suitable output capacitor (say a 2.2 uF Tantalum with a one Ohm ESR) which should be perfectly stable..... and then somebody adds a few 0.01 uF ceramic bypass capacitors on the output rail to help reduce noise. Common sense tells us there should be no problem, after all a few 0.01 uF caps in parallel with a 2.2 uF cap should have no effect. The larger Tantalum should swamp out the effects of a smaller capacitor... or would it?

Unfortunately, most LDO's can tolerate only a small amount of ceramic capacitance (like a few thousand pico Farads) placed directly on the output even when a good Tantalum capacitor is already there. To understand why this is true, it must be remembered that the PNP pass transistor has a relatively high output impedance and looks like a current source driving the output capacitors. This means that two capacitors in parallel with very different ESR values will form a distinct pole/zero set for each individual capacitor. Recalling that the frequency of the pole and zero for EACH capacitor connected to the output can be closely approximated by:

fp = 1 / (2 * pi * RL * COUT)

fz = 1 / (2 * pi * ESR * COUT)

We can now examine a real-time example of how the small ceramic caps can cause oscillation using the LP2980 which is a 50 mA LDO built on a high-performance bipolar process. Open loop gain is assumed to be about 80dB and the fixed-frequency pole provided by the error amplifier is set at about 200 Hz. An output cap of 2.2uF Tantalum will be used and an ESR value of 1 Ohm will be assumed. Operating at 2.5V out with 50mA load current, that means RL = 50 Ohms. From the above equations, the Tantalum capacitor's load pole will be at 1.4 kHz and the ESR zero will be at 72 kHz. Figure 7 shows the gain and phase plot of this regulator.

Clearly, without ceramic capacitors the circuit is quite stable because it has a phase margin of about 50 degrees. Next, we will study what happens if we add four ceramic bypass capacitors with a value of 0.01 uF each. We will assume an ESR of about 5 milli Ohms for the ceramic capacitors. Since all four of the ceramic capacitors are electrically equivalent, we will model them as a single ceramic capacitor of 0.04 uF. This will form a pole at 79 kHz and a zero at about 300 MHz. Most engineers can see what's coming at this point: the pole from the ceramic capacitors almost exactly cancels out the zero of the Tantalum ESR which is providing the phase lead required to make the loop stable (Figure 8 shows the effects of adding the ceramic capacitors).

Since the pole from the ceramics wipes out the Tantalum's ESR zero, the two lower frequency poles from the error amplifier and the Tantalum output capacitor will cause a negative 180 degree phase shift and the loop will be completely unstable. It should be noted that in bench testing, this particular device could be made to oscillate with values of ceramic bypass capacitance between 0.002 and 0.003 uF, so it is not necessary to drop the pole exactly on top of the zero to get the phase margin low enough to make the loop oscillate (just getting close can do it).

That explains why we generally recommend against putting ceramics on the output of “Tantalum-only” LDO regulators. If you must use ceramics, keep the amount of capacitance to a minimum and move them physically as far as possible from the output of the LDO, since trace inductance will help to decouple the effect of the ceramic capacitors. This particular susceptibility to small ceramic capacitors is not unique to National Semiconductor's LDO regulators, as nearly all PNP (or P-FET) LDO regulators have similar control loops and similar characteristics in regards to loop gain and phase. They are generally only stable with ceramic capacitors if specifically designed to be (see next section).

LDO's Which Are Stable With Ceramic Output Capacitors

In the late 1990's, ceramic capacitors passed Tantalums as the most optimum choice for capacitor values in the 1 uF to 5 uF range in terms of size, cost, availability, and overall electrical performance. This was due primarily to the development of new ceramic materials which made it possible to fabricate low-volatge ceramics which were extremely small and cheap in values as high as 10 uF.

Because of this, customers demanded LDO regulators be made which were stable using ceramic output capacitors. About 4 years ago, National Semiconductor brought out a low-noise, high performance LDO called the LP2985 which met these requirements. The method used to make the part ceramic-stable was to alter the error amplifier compensation so that it had both the dominant (fixed) pole traditionally used, and also a zero to take the place of the ESR zero which was formerly provided by the Tantalum output capacitor (see Figure 9). A resistor is placed in series with the compensation capacitor in the feedback loop of the error amplifier which adds a zero to the loop gain. Using this technique, the control loop is stable with output capacitance ESR values down to zero Ohms.

Transient response

An article about the usage of capacitors in the design of linear and switching regulators would not be complete without some information on transient response, defined as the regulator's ability to hold it's output in regulation when the load current changes abruptly. Transient response became a very important aspect of design about seven or eight years back as the operating speeds of microprocessor chips increased, demanding both higher current from their supplies and also requiring rails that would stay solid when hit with demands for high peak currents that were virtually instantaneous in time. One particular power supply specification I read required the output to stay within 3 percent of nominal when the load current changed from zero to 15A in 100 nano seconds. That was pretty scary, but the demands made on the CPU power supply today (and in the near future) will make that look like the good old days.

A few years back, I attended a presentation from another semiconductor manufacturer who was explaining about how their new regulator was going to solve the transient response problem: “The response time of this part is so fast you won't even need capacitors!” The truth is that capacitors were, are and always will be required to provide power in systems with very fast changing load currents. Faster responding regulators (or converters) do provide a way to reduce the total amount of capacitance by shifting more of the energy load from the regulator's output capacitors to the input capacitors. The following information should give the designer a better understanding of the various elements of the transient response design parameters.

The basics of a load transient

The equivalent circuit to understand a load transient is shown in Figure 10. The circuit elements labeled “Lp” represent parasitic inductances in either the PCB traces, component leads, or inductance internal to the capacitors. CBYP is shown without any value of ESR because it is assumed it will be a ceramic capacitor and the ESR will be negligible. It will also be assumed that the load is drawing zero or negligible current, then at time t = 0, the load current steps to full load in a very fast rise time. This will result in an output voltage excursion as shown.

Inductance effects

In the initial part of the load transient where the load current is increasing very rapidly, most of the current will be provided by the capacitor shown as CBYP (which may actually be a lot of capacitors in parallel). These are typically ceramic capacitors because they must have absolute minimum ESR (equivalent series resistance) and ESL (equivalent series inductance). To see why inductance must be minimized, it should be understood that a current changing in an inductor forces a voltage drop across it given by:

V = L * (dI/dt)

For this example we will assume that the current rises from zero to 15A in 100 ns. We will assume the output rail voltage to the load is 2.5V, with an allowable worst-case deviation specification of --3 percent. Given these parameters, the maximum inductance between the CBYP and load terminal (including internal ESL and PCB trace inductance) is a maximum of 0.5 nH (or 500 pH).

Board designers minimize inductance through layout. A good example is the CPU on a typical mother board. The CPU chip is plugged into a “cavity” socket which has an air gap under the CPU chip. This space is usually filled with dozens of ceramic capacitors which supply current to the load during very fast transients. Of course since these are ceramics, the total capacitance which can be practically mounted in this small space is limited. The main current to support the load transient must be provided by the output capacitor COUT.

Bulk capacitance

Before the regulator loop registers the need for increased current and starts supplying it, the majority of the current supplied to the load must be provided by COUT, sometimes called bulk capacitance. These are normally aluminum electrolytic capacitors, which are optimized for low ESR and very low high-frequency impedance (which means they are more expensive than standard AL caps). On a motherboard, these caps are usually sitting right next to the CPU socket. Note that as the current begins to flow out of COUT, the voltage at the terminal of COUT will be decreased by the value of:

VESR = IL * ESR.

This is the reason the output voltage shows a “step” down in voltage right after the “L” spike occurs. As COUT continues to supply current, the voltage across COUT discharges at a rate given by:

IL = C * (dV/dt)

We can estimate how much bulk capacitance would be needed in this particular example if we assume the loop will kick the power converter or regulator “ON” in about 20 us. Further, we will assume that the output may only discharge 3% of the 2.5V rail in those 20 us (the ESR drop will be neglected for this calculation). If the 15A current is to be delivered for 20 us and the voltage drop not more than 75 mV, then a capacitance of at least 4000 uF must be provided.

Designing in this much capacitance using very good Al capacitors is fairly costly, and highlights the reason faster regulators and converters are so important in designs that must maintain regulation when hit by fast-rising, high-current transients. The amount of bulk capacitance required at COUT is directly proportional to how long it takes the regulator or power converter to turn on the power device and supply load current from CIN. By transferring more of the load support back to CIN, the total amount of bulk capacitance required by the system is reduced since a larger voltage change at CIN can be allowed because the regulator will correct for it.